27.10.2 Protection of APB Clients

To be able to configure the protection mode required for accessing a particular peripheral bus client connected behind the system-to-peripheral bus (AHB/APB Bridge), the MATRIX features three 32-bit Protected Peripheral Select x Registers. Some of these bits may have been set by design to a Privileged or a User value, when others are programmed by software (see Protected Peripheral Select x Registers).

The system-to-peripheral bus bridge compares the incoming host request protection bit with the required protection for the selected peripheral, and accepts or denies access. In the last case, its bus error response is internally flagged in the MATRIX Host Error Status Register; the offending address is registered in the Host Error Address Registers.