36.5.2 Power Management

The SLCDC is clocked by the slow clock (SLCK). All the timings are based upon a typical value of 32 kHz for SLCK.

The LCD segment/common pad buffers are supplied by the VDDLCD domain when they are driven by the SLCDC; otherwise they are supplied by VDD3V3. Refer to SLCDC Mode Register and SLCDC Segment Map Register 0.