36.8.2 SLCDC Mode Register
This register can only be written if the WPEN bit is cleared in the Write Protection Mode register and the bit DFFRZS is cleared in the Status register.
| Name: | SLCDC_MR |
| Offset: | 0x4 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| LPMODE | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| BIAS[1:0] | BUFTIME[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SEGSEL[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| COMSEL[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
Bit 24 – LPMODE Low-Power Mode
Processed at beginning of next frame.
| Value | Description |
|---|---|
| 0 | Normal mode. |
| 1 | Low-power waveform is enabled. |
Bits 21:20 – BIAS[1:0] LCD Display Configuration
For safety reasons, can be configured when SLCDC is disabled.
| Value | Name | Description |
|---|---|---|
| 0 | STATIC | Static |
| 1 | BIAS_1_2 | Bias 1/2 |
| 2 | BIAS_1_3 | Bias 1/3 |
| 3 | BIAS_1_4 |
Bias 1/4 |
Bits 19:16 – BUFTIME[3:0] Buffer On-Time
(Processed at beginning of next frame)
| Value | Name | Description |
|---|---|---|
| 0 | OFF | Nominal drive time is 0% of SLCK period |
| 1 | X2_SLCK_PERIOD | Nominal drive time is 2 periods of SLCK clock |
| 2 | X4_SLCK_PERIOD | Nominal drive time is 4 periods of SLCK clock |
| 3 | X8_SLCK_PERIOD | Nominal drive time is 8 periods of SLCK clock |
| 4 | X16_SLCK_PERIOD | Nominal drive time is 16 periods of SLCK clock |
| 5 | X32_SLCK_PERIOD | Nominal drive time is 32 periods of SLCK clock |
| 6 | X64_SLCK_PERIOD | Nominal drive time is 64 periods of SLCK clock |
| 7 | X128_SLCK_PERIOD | Nominal drive time is 128 periods of SLCK clock |
| 8 | PERCENT_50 | Nominal drive time is 50% of SLCK period |
| 9 | PERCENT_100 | Nominal drive time is 100% of SLCK period |
Bits 13:8 – SEGSEL[5:0] Selection of the Number of Segments
For safety reasons, can be configured when SLCDC is disabled.
SEGSEL must be programmed with the number of segments of the display panel minus 1.
If segment remapping function is not used (i.e., SLCDC_SMR0 equal 0) the SEGn [n = 0..30] I/O pins where n is greater than SEGSEL are forced to be driven by digital function. When segments remapping function is used, SEGn pins are driven by SLCDC only if corresponding PIXELn configuration bit is set in SLCDC_SMR0.
Bits 2:0 – COMSEL[2:0] Selection of the Number of Commons
For safety reasons, can be configured when SLCDC is disabled.
| Value | Name | Description |
|---|---|---|
| 0 | COM_0 | COM0 is driven by SLCDC, COM1:7 are driven by digital function |
| 1 | COM_0TO1 | COM0:1 are driven by SLCDC, COM2:7 are driven by digital function |
| 2 | COM_0TO2 | COM0:2 are driven by SLCDC, COM3:7 are driven by digital function |
| 3 | COM_0TO3 | COM0:3 are driven by SLCDC, COM4:7 are driven by digital function |
| 4 | COM_0TO4 |
COM0:4 are driven by SLCDC, COM5:7 are driven by digital function |
| 5 | COM_0TO5 |
COM0:5 are driven by SLCDC, COM6:7 are driven by digital function |
| 6 | COM_0TO6 |
COM0:6 are driven by SLCDC, COM7:7 are driven by digital function |
| 7 | COM_0TO7 |
COM0:7 are driven by SLCDC, COM8:7 are driven by digital function |