36.8.10 SLCDC Segment Map Register 0
This register can only be written if the WPEN bit is cleared in the Write Protection Mode register and the bit FRZS is cleared in the Status register.
| Name: | SLCDC_SMR0 |
| Offset: | 0x30 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| LCD31 | LCD30 | LCD29 | LCD28 | LCD27 | LCD26 | LCD25 | LCD24 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| LCD23 | LCD22 | LCD21 | LCD20 | LCD19 | LCD18 | LCD17 | LCD16 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| LCD15 | LCD14 | LCD13 | LCD12 | LCD11 | LCD10 | LCD9 | LCD8 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LCD7 | LCD6 | LCD5 | LCD4 | LCD3 | LCD2 | LCD1 | LCD0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – LCDx LCD Segment Mapped on SEGx I/O Pin
For safety reasons, can be configured when SLCDC is disabled.
| Value | Description |
|---|---|
| 0 |
The corresponding I/O pin is driven either by SLCDC or digital function, depending on the SEGSEL field configuration in SLCDC_MR. |
| 1 |
An LCD segment is driven on the corresponding I/O pin. |