6.2 Power-Up Specification

All functionalities and DC specifications are specified for a V_DD ramp rate greater than 1V per 100 ms (0V to 3V in less than 300 ms).

When V_DD drops from the operating voltage to below the minimum V_DD threshold at power-down, all operations are disabled and the device does not respond to commands. Data corruption may result if a power-down occurs while a Write Registers, Program, or Erase operation is in progress (see Figure 6-2).

Table 6-3. Recommended System Power-Up/Down Timings
Symbol	Parameter	Min.	Max.	Units
T_PU⁽¹⁾	V_DD minimum to/CE low for Read/Write operation	1.5	—	ms
T_PD⁽¹⁾	Power-down duration	100	—	µs
V_OFF⁽¹⁾	V_DD off	—	1	V

Note:

This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Figure 6-1. Power-Up Timing Diagram

Figure 6-2. Power-Down and Voltage Drop Diagram

Note: The Chip Enable pin must track the V pin at power-up and power-down. A pull-up resistor (10K recommended) between the CE# pin and V pin is required.