6.4 AC Characteristics

Table 6-8. AC Characteristics
Symbol	Parameter	Industrial (I): T_AMB = -40°C to +85°C Industrial Plus (V): T_AMB = -40°C to +105°C
Symbol	Parameter	Min.	Max.	Units	Conditions
F_CLK	Clock Frequency for all commands except Read (03H) and DTR instructions	—	166	MHz
T_CLK	Serial Clock Period	—	6.024	ns
T_SCKH	Serial Clock High Time	45% of clock period	—	ns	Note 1
T_SCKL	Serial Clock Low Time	45% of clock period	—	ns	Note 1
T_SCKR	Serial Clock Rise Time (Slew Rate)	0.1	—	V/ns	Note 2 and Note 7
T_SCKF	Serial Clock Fall Time (Slew Rate)	0.1	—	V/ns	Note 2 and Note 7
T_CES	CE# Active Setup Time	5	—	ns	Note 3
T_CEH	CE# Active Hold Time	5	—	ns	Note 3
T_CHS	CE# Not Active Setup Time	5	—	ns	Note 3
T_CHH	CE# Not Active Hold Time	5	—	ns	Note 3
T_CPH1	CE# High Time (Read)	7	—	ns
T_CPH2	CE# High Time (Erase, Program or Write)	30	—	ns
T_CHZ	CE# High to High-Z Output	—	6	ns	Note 7
T_DS	Data In Setup Time	2	—	ns
T_DH	Data In Hold Time	3	—	ns
T_HLS	HOLD# Low Setup Time	5	—	ns
T_HHSS	HOLD# High Setup Time	5	—	ns
T_HLH	HOLD# Low Hold Time	5	—	ns
T_HHH	HOLD# High Hold Time	5	—	ns
T_HZ	HOLD# Low to High-Z Output	—	6	ns	Note 7
T_LZ	HOLD# High to Low-Z Output	—	6	ns	Note 7
T_OH	Output Hold from SCK Change	1	—	ns
T_V	Output Valid from SCK	—	7/6	ns	Note 4
T_WPS	Write Protect Setup Time prior to CE# Low	20	—	ns	Note 5
T_WPH	Write Protect Hold Time after CE# High	100	—	ns	Note 5
T_SBR1	CE# High to Standby Mode without Read ID	—	20	µs	Note 7
T_SBR2	CE# High to Standby Mode with Read ID	—	20	µs	Note 7
T_SUS	CE# High to next instruction after Suspend	—	22	µs	Note 7
T_LRS	Latency between Resume and next Suspend	50	—	µs	Note 7
T_WSR	Write Status Register Time (Nonvolatile)	—	15	ms
T_RST	Reset pin low period to reset the device	1	—	µs	Note 6 and Note 7
T_RECW	Software/Hardware Reset latency (device in write operation - Program, Suspend)	—	28	µs
T_RECE	Software/Hardware Reset latency (device in write operation - Erase)	—	12	ms
T_RECR	Software Reset/Hardware latency (device not in write operation)	—	0.3	µs
T_DPD	CE# High to Power Down Mode	—	3	µs	Note 7
Note: The clock high or clock low must be greater than or equal to 45% of clock period P_CLK. P_CLK=1/f_CLK (maximum). Maximum rise and fall times may be limited by the T_SCKH and T_SCKL requirements. Relative to SCK. Loading: 30 pF/15 pF. Applicable only as a constraint for a Write Status Register instruction when SRP[1:0] = (0,1). The device can be reset using a shorter t_RESET (down to a few hundred ns); however, a minimum of 1 µs is recommended to ensure reliable operation. Value guaranteed by design and/or characterization; not 100% tested in production.

Figure 6-3. Serial Input Timing

Figure 6-4. Serial Output Timing (STR)

Figure 6-5. Hold Timing

Figure 6-6. Hardware Reset Timing Diagram

Table 6-9. Reset Timing Parameters
TR(i)	Parameter	Minimum	Maximum	Units
T_RECR	Reset to Read (non-data operation)	—	0.3	µs
T_RECW	Reset Recovery from Program or Suspend	—	28	µs
T_RECE	Reset Recovery from Erase	—	12	ms
T_RST	Reset Pulse Width (Hardware Reset)	1	—	µs
T_RHZ	Reset to High-Z Output	—	—	ns

Figure 6-7. Reset Timing Diagram

Note: C[1:0] = 66H; C[3:2] = 99H

Figure 6-8. AC Input Output Reference Voltage

Note:

AC test inputs are driven at V_IHT (0.9V_DD) for a logic 1 and V_ILT (0.1V_DD) for a logic 0. Measurement reference points for inputs and outputs are V_HT (0.5V_DD) and V_LT (0.5V_DD). Input rise and fall times (10%⇔90%) are < 5 ns.
V_HT = V_HIGH Test; V_LT = V_LOW Test; V_IHT = V_INPUT HIGH Test; V_ILT = V_INPUT LOW Test.