3.2 External INT0, INT1 Pin Configuration

To enable external INT0, INT1 pin interrupt function enable, EICRA (external interrupt control register A) register should be configured to select the sensing mode – falling edge, rising edge, logic change, or low level, and enable INT0, INT1 interrupt request bits of the EIMSK (external interrupt mask register).

Figure 3-1. External Interrupt Control Register A

Bits 3:2 – ISC1n: Interrupt Sense Control 1 [n = 1:0]

ValueDescription
00The low level of INT1 generates an interrupt request
01Any logical change on INT1 generates an interrupt request
10The falling edge of INT1 generates an interrupt request
11The rising edge of INT1 generates an interrupt request

Bits 1:0 – ISC0n: Interrupt Sense Control 0 [n = 1:0]

ValueDescription
00The low level of INT0 generates an interrupt request
01Any logical change on INT0 generates an interrupt request
10The falling edge of INT0 generates an interrupt request
11The rising edge of INT0 generates an interrupt request
Figure 3-2. External Interrupt Mask Register

Bit 1 – INT1: External Interrupt Request 1 Enable.

Bit 0 – INT0: External Interrupt Request 0 Enable.