8.2.1 System Power-Up

At power-up, from a power supply sequencing perspective, the SAM9X75 SOM Series power supplies are categorized into seven independent groups:
  • 5V_MAIN (main supply)
  • VDDBU (backup group)
  • VDD_3V3 (internal periphery group) containing VDDIN33, VDDQSPI, VDDIOP2 and VDDNF inputs
  • External VDD_PERIPH (external periphery group) containing VDDANA, VDDIOP0, and VDDIOP1 inputs
  • VDDLVDS and VDDMIPI (video group)
  • VDDIODDR (memory group)
  • VDDCORE (core group)

Figure 8-2 shows the recommended power-up sequence.

Note:
  • VDDBU
    • When supplied from a precharged storage element (battery, supercapacitor or micro-battery), VDDBU is an always-on supply input and is therefore not part of the power supply sequencing.
    • When no storage element is used on VDDBU in the application, VDDBU must be tied to VDD_3V3.
    • When a supercapacitor or a micro-battery is used in the application to power VDDBU in Backup mode, this element must be isolated from VDDBU during its (slow) charge, so that VDDBU closely follows VDD_3V3. In Table   1, the parameter t1 limits the delay to establish VDDBU after VDD_3V3.
  • VDDOUT25 is the output of the internal 2.5V regulator, and therefore there is no power supply requirement on this pin.
Figure 8-2. Recommended Power-Up Sequence
Note:
  1. VDD_3V3 is generated internally by the MCP16502 PMIC and directly supplies the internal periphery group.
  2. VDDIODDR is generated internally by the MCP16502 PMIC and directly supplies the memory group.
  3. This group is supplied externally and requires no specific order. Only timing t3 must be respected.
  4. VDDOUT25 is generated internally by the SAM9X75 SiP device and can be used to directly supply the internal video group.
  5. VDDCORE is generated internally by the MCP16502 PMIC and directly supplies the core group.
  6. The RESET general signal is generated internally by the MCP16502 PMIC and is distributed to the whole system.
Table 8-2. Power-Up Timing Requirements
SymbolParameterConditions(1)MinTyp(2)MaxUnit
t0nSTRT deglitch timenSTRT pin falling edge–0.5–ms
t1VDDBU delayDelay from established VDD_3V3 to established VDDBU––0.2ms
t2VDD_3V3 to memory group delayDelay from established VDD_3V3 to VDDIODDR supply turn-on–8–ms
t3VDD_3V3 to external periphery group delay(3)Delay from established VDD_3V3 to external periphery group established supply0–t2ms
t4Periphery group to VDDCORE delayDelay from periphery group established supply to VDDCORE supply turn-on–4–ms
t5Reset delay at power-upFrom established VDDCORE to NRST high–16–ms
Note:
  1. The term "established" refers to a power supply having reached 90% of its final value.
  2. Typical timing values can be programmed in MCP16502 registers (RSTDLY[2:0]), but they must follow the timing sequence required by the SAM9X75 SiP device.
  3. If one of the power inputs of the group is supplied externally, the power must be applied at the same time or after the presence of VDD_3V3 and before the presence of VDDIODDR.