7.2.4 PIOD Pin List
| Pad No. | Power Rail | I/O Type | Primary | Alternate Signal | PIO Peripheral | Reset State(1) | Note | |||
|---|---|---|---|---|---|---|---|---|---|---|
| Signal | Type | Func | Signal | IO Set | Signal, Dir, PU, PD, HiZ, ST | |||||
| – | VDD_3V3 | GPIO | PD0 | GPIO | – | A | NANDOE | 1 | PIO, I, PU | Used for NAND Flash(2) |
| – | VDD_3V3 | GPIO | PD1 | GPIO | – | A | NANDWE | 1 | PIO, I, PU | Used for NAND Flash(2) |
| – | VDD_3V3 | GPIO | PD2 | GPIO | – | A | A21/NANDALE | 1 | A21, O, PD | Used for NAND Flash(2) |
| – | VDD_3V3 | GPIO | PD3 | GPIO | – | A | A22/NANDCLE | 1 | A22, O, PD | Used for NAND Flash(2) |
| 18 | VDD_3V3 | GPIO | PD4 | GPIO | – | A | NCS2/NANDCS | 1 | PIO, I, PU | Used for NAND Flash(2) |
| – | VDD_3V3 | GPIO | PD5 | GPIO | – | – | – | – | PIO, I, PU | Used for Ethernet PHY interrupt(2) |
| – | VDD_3V3 | GPIO | PD6 | GPIO | – | A | NANDDAT0 | 1 | PIO, I, PU | Used for NAND Flash(2) |
| – | VDD_3V3 | GPIO | PD7 | GPIO | – | A | NANDDAT1 | 1 | PIO, I, PU | Used for NAND Flash(2) |
| – | VDD_3V3 | GPIO | PD8 | GPIO | – | A | NANDDAT2 | 1 | PIO, I, PU | Used for NAND Flash(2) |
| – | VDD_3V3 | GPIO | PD9 | GPIO | – | A | NANDDAT3 | 1 | PIO, I, PU | Used for NAND Flash(2) |
| – | VDD_3V3 | GPIO | PD10 | GPIO | – | A | NANDDAT4 | 1 | PIO, I, PU | Used for NAND Flash(2) |
| – | VDD_3V3 | GPIO | PD11 | GPIO | – | A | NANDDAT5 | 1 | PIO, I, PU | Used for NAND Flash(2) |
| – | VDD_3V3 | Ground | PD12 | Ground | – | A | NANDDAT6 | 1 | PIO, I, PU | Used for NAND Flash(2) |
| – | VDD_3V3 | Ground | PD13 | Ground | – | A | NANDDAT7 | 1 | PIO, I, PU | Used for NAND Flash(2) |
| – | VDD_3V3 | Ground | PD14 | Ground | – | A | NWAIT/NANDRDY | 1 | PIO, I, PU | Used for NAND Flash(2) |
Note:
- Signal = ‘PIO’ if GPIO; Dir = Direction; PU = Pull-up; PD = Pull-down; HiZ = High impedance; ST = Schmitt Trigger.
- This feature is fixed due to the SAM9X75 SOM Series internal connection.