14.8.4 Peripheral Channel Control

PCHTRLm controls the settings of Peripheral Channel number m (m=[47:0]).

Name:	PCHCTRLm
Offset:	0x80 + m*0x04 [m=0..47]
Reset:	0x00000000
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	WRTLOCK	CHEN			GEN[3:0]
Access	R/W	R/W			R/W	R/W	R/W	R/W
Reset	0	0			0	0	0	0

Bit 7 – WRTLOCK Write Lock

After this bit is set to '1', further writes to the PCHCTRLm register will be discarded. The control register of the corresponding Generator n (GENCTRLn), as assigned in PCHCTRLm.GEN, will also be locked. It can only be unlocked by a Power Reset.

Note that Generator 0 cannot be locked.

Value	Description
0	The Peripheral Channel register and the associated Generator register are not locked
1	The Peripheral Channel register and the associated Generator register are locked

Bit 6 – CHEN Channel Enable

This bit is used to enable and disable a Peripheral Channel.

Value	Description
0	The Peripheral Channel is disabled
1	The Peripheral Channel is enabled

Bits 3:0 – GEN[3:0] Generator Selection

This bit field selects the Generator to be used as the source of a peripheral clock, as shown in the table below:

Table 14-7. Generator Selection
Value	Description
0x0	Generic Clock Generator 0
0x1	Generic Clock Generator 1
0x2	Generic Clock Generator 2
0x3	Generic Clock Generator 3
0x4	Generic Clock Generator 4
0x5	Generic Clock Generator 5
0x6	Generic Clock Generator 6
0x7	Generic Clock Generator 7
0x8	Generic Clock Generator 8
0x9	Generic Clock Generator 9
0xA	Generic Clock Generator 10
0xB	Generic Clock Generator 11

Table 14-8. Reset Value after a User Reset or a Power Reset
Reset	PCHCTRLm.GEN	PCHCTRLm.CHEN	PCHCTRLm.WRTLOCK
Power Reset	0x0	0x0	0x0
User Reset	If WRTLOCK = 0 : 0x0 If WRTLOCK = 1: no change	If WRTLOCK = 0 : 0x0 If WRTLOCK = 1: no change	No change

A Power Reset will reset all the PCHCTRLm registers.

A User Reset will reset a PCHCTRL if WRTLOCK=0, or else, the content of that PCHCTRL remains unchanged.

The PCHCTRL register Reset values are shown in the table below, PCHCTRLm Mapping.

Table 14-9. PCHCTRLm Mapping
index(m)	Name	Description
0	GCLK_OSCCTRL_DFLL48	DFLL48 input clock source
1	GCLK_OSCCTRL_FDPLL0	Reference clock for FDPLL0
2	GCLK_OSCCTRL_FDPLL1	Reference clock for FDPLL1
3	GCLK_OSCCTRL_FDPLL0_32K GCLK_OSCCTRL_FDPLL1_32K GCLK_SDHC0_SLOW GCLK_SDHC1_SLOW GCLK_SERCOM[0..7]_SLOW	FDPLL0 32KHz clock for internal lock timer FDPLL1 32KHz clock for internal lock timer SDHC0 Slow SDHC1 Slow SERCOM[0..7] Slow
4	GCLK_EIC	EIC
5	GCLK_FREQM_MSR	FREQM Measure
6	GCLK_FREQM_REF	FREQM Reference
7	GCLK_SERCOM0_CORE	SERCOM0 Core
8	GCLK_SERCOM1_CORE	SERCOM1 Core
9	GCLK_TC0, GCLK_TC1	TC0, TC1
10	GCLK_USB	USB
22:11	GCLK_EVSYS[0..11]	EVSYS[0..11]
23	GCLK_SERCOM2_CORE	SERCOM2 Core
24	GCLK_SERCOM3_CORE	SERCOM3 Core
25	GCLK_TCC0, GCLK_TCC1	TCC0, TCC1
26	GCLK_TC2, GCLK_TC3	TC2, TC3
27	GCLK_CAN0	CAN0
28	GCLK_CAN1	CAN1
29	GCLK_TCC2, GCLK_TCC3	TCC2, TCC3
30	GCLK_TC4, GCLK_TC5	TC4, TC5
31	GCLK_PDEC	PDEC
32	GCLK_AC	AC
33	GCLK_CCL	CCL
34	GCLK_SERCOM4_CORE	SERCOM4 Core
35	GCLK_SERCOM5_CORE	SERCOM5 Core
36	GCLK_SERCOM6_CORE	SERCOM6 Core
37	GCLK_SERCOM7_CORE	SERCOM7 Core
38	GCLK_TCC4	TCC4
39	GCLK_TC6, GCLK_TC7	TC6, TC7
40	GCLK_ADC0	ADC0
41	GCLK_ADC1	ADC1
42	GCLK_DAC	DAC
44:43	GCLK_I2S	I2S
45	GCLK_SDHC0	SDHC0
46	GCLK_SDHC1	SDHC1
47	GCLK_CM4_TRACE	CM4 Trace