Compliant with Inter-IC Sound
(I2S) bus specification
Supported data formats:
32-, 24-, 20-, 18-, 16-, and
8-bit mono or stereo format
16- and 8-bit compact stereo
format, with left and right samples packed in the same word to reduce data
transfers
Supported data frame formats:
2-channel I2S with
Word Select
1- to 8-slot Time Division Multiplexed (TDM) with
Frame Sync and individually enabled slots
1- or 2-channel Pulse Density
Modulation (PDM) reception for MEMS microphones
1-channel burst transfer with
non-periodic Frame Sync
2 independent Clock
Units handling either the same clock or separate clocks for the Serializers:
Suitable for a wide range of
sample frequencies fs, including 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, and
192kHz
16×fs to 1024×fs
Host Clock generated for external audio CODECs
Host, client, and controller modes:
Host: Data received/transmitted
based on internally-generated clocks. Output Serial Clock on SCKn pin, Host Clock
on MCKn pin, and Frame Sync Clock on FSn pin
Client: Data received/transmitted
based on external clocks on Serial Clock pin (SCKn) or Host Clock pin (MCKn)
Controller: Only output
internally generated Host clock (MCKn), Serial Clock (SCKn), and Frame Sync Clock
(FSn)
Individual enabling and disabling of
Clock Units and Serializers
DMA interfaces for each Serializer
receiver or transmitter to reduce processor overhead:
Either one DMA channel for all
data slots or
One DMA channel per data channel
in stereo
Smart Data Holding register management to avoid data slots mix after overrun or underrun
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
