45.6.3.4 DMA Sequencing
The ADC can sequence a series of conversion. When DMA sequencing is enabled, a set of ADC configuration registers can be automatically refreshed using the DMA controller.
DMA Sequencing is enabled when at least one bit in the DMA Sequence Control register (DSEQCTRL) is '1'.
When this is the case, the BUSY status bit in the DMA Sequential Status register (DSEQSTAT.BUSY) is set to '1'.
Disabling DMA Sequencing
- The ADC is disabled (CTRLA.ENABLE = 0).
- The ADC is reset (CTRLA.SWRST = 1).
- The DMA Sequence Control register (DSEQCTRL) is written '0' and the ongoing DMA sequence is completed.
- The DMA Sequencing Stop bit in Input Control register is '1' (INPUTCTRL.DSEQSTOP = 1) and the ongoing DMA sequence is complete. One additional measurement will be done before the ADC is disabled.
When the DMA sequencing is disable, the BUSY status bit in the DMA Sequential Status register (DSEQSTAT.BUSY) is cleared and the DMA trigger generation is disabled.
Note that if the DSEQCTRL register is written to a non-zero value, the DSEQSTOP bit in the INPUTCTRL register will be cleared and the sequencing operation will not be stopped.
Restarting DMA Sequencing
- Write the DSEQSTOP bit in Input Control register to zero (INPUTCTRL.DSEQSTOP = 0)
- Apply a FLUSH software command (SWTRIG.FLUSH = 1)
- Enable the flush event (EVCTRL.FLUSHEI). The sequence will restart when the flush event is received
DMA Sequencing Operation
Each ADC register that is part of the DMA sequencing has a separate enable bit in the DSEQCTRL register to indicate that this field should be part of the DMA sequencing. When an enable bit in DSEQCTRL is '1', the respective register will be updated when an access to DSEQDATA is decoded.
- Input Control or Control B bits in DMA Sequential Control register is '1' (DSEQCTRL.INPUTCTRL=1 or DSEQCTRL.CTRLB=1)
- Reference Control, Sampling Time Control or Average Control bits in DMA Sequential Control register is set (DSEQCTRL.REFCTRL=1, DSEQCTRL.AVGCTRL=1 or DSEQCTRL.SAMPCTRL=1)
- Window Monitor Upper Threshold or Window Monitor Lower Threshold bits in DMA Sequential Control register is set (DSEQCTRL.WINUT=1 or DSEQCTRL.WINLT=1)
- Offset Correction or Gain Correction bits in DMA Sequential Control register is set (DSEQCTRL.GAINCORR=1 or DSEQCTRL.OFFSETCORR=1)
| Condition | Value | Action when DMA writes to DSEQDATA |
|---|---|---|
| DSEQSTAT.INPUTCTRL or DSEQSTAT.CTRLB | 0 |
|
| 1 |
| |
| DSEQSTAT.REFCTRL or DSEQSTAT.AVGCTRL or DSEQSTAT.SAMPCTRL | 0 |
|
| 1 |
| |
| DSEQSTAT.WINLT or DSEQSTAT.WINUT | 0 |
|
| 1 |
| |
| DSEQSTAT.GAINCORR or DSEQSTAT.OFFSETCORR | 0 |
|
| 1 |
|
The DMA Sequential Status register (DSEQSTAT) stores the remaining registers to be updated by the DMA. During a sequence and when a write access to the DSEQDATA register is detected, the DSEQSTAT bits which were source of the corresponding DSEQ trigger will be cleared. When all DSEQSTAT bits are zero (except BUSY bit), the DSEQCTRL register bits (except AUTOSTART) are copied into the DSEQSTAT register and a new DMA sequence is started when a new ADC conversion starts.
DMA Descriptor Setup and Data Memory Organization
- Select 32-bit beat size transfer (DMAC.BTCTRL.BEATSIZE=WORD).
- Enable the source address increment options (DMAC.BTCTRL.SRCINC = 1, DMAC.BTCTRL.STEPSEL = SRC, DMAC.BTCTRL.STEPSIZE = X1).
- Disable the destination address increment (DMAC.BTCTRL.DSTINC=0).
- Set the block transfer count value (DMAC.BTCNT).
- Set the block transfer source address (DMAC.SRCADDR), as described in the DMAC Addressing section. The address corresponds to the memory section from where the DMA reads the data.
- Select the ADC.DSEQDATA address as value for the block transfer destination address (DMAC.DSTADDR = ADC.DSEQDATA address).
- Select the channel single transfer type (DMAC.CHCTRLA.BURSTLEN=SINGLE)
- Select the channel burst trigger action (DMAC.CHCTRLA.TRIGACT=BURST)
- Select the ADC DMA Sequencing trigger as channel trigger source (DMAC.CHCTRLA.TRIGSRC=DSEQ)
- Enable optional channel interrupts (DMAC.CHINTENSET)
- Enable the corresponding DMA channel (DMAC.CHCTRLA.ENABLE)
When an ADC condition is enabled to trigger a DMA transfer, one word (32-bit) will be read by the DMA from the memory source location. Since the source address is incrementing by 0x1, the data memory must be organized in a contiguous memory area. As consequence, if an ADC group of registers does not generate any DMA trigger, no data must be reserved in the memory area for this register group. The next figure shows an example of memory organization when all ADC registers are part of the sequence, and a second example where WINLT and WINUT registers are not part of the sequence.
Automatic Start Conversion
By default, a new conversion starts when a new start software or event trigger is received. It is also possible to automatically enable an ADC conversion by writing '1' to the AUTOSTART bit in DSEQCTRL register (DSEQCTRL.AUTOSTART). When set, the ADC automatically starts a new conversion when a DMA sequence is complete.