26.8.8 Undefined Access Status Register
| Name: | UASR |
| Offset: | 0x20 |
| Reset: | 0x0 |
| Property: | Read-Only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| URAT[2:0] | |||||||||
| Access | R | R | R | ||||||
| Reset | 0 | 0 | 0 | ||||||
Bits 2:0 – URAT[2:0] Undefined Register Access Trace
Only the first Undefined Register Access Trace is available through the URAT field.
The URAT field is only reset by the Software Reset bit in the Control register (CTRL.SWRST).
| Value | Name | Description |
|---|---|---|
| 0 | UNSPEC_STRUCT_MEMBER | Unspecified structure member set to '1' detected when the descriptor is loaded. |
| 1 | ICM_CFG_MODIFIED | CFG modified during active monitoring. |
| 2 | ICM_DSCR_MODIFIED | DSCR modified during active monitoring. |
| 3 | ICM_HASH_MODIFIED | HASH modified during active monitoring |
| 4 | READ_ACCESS | Write-only register read access Only the first Undefined Register Access Trace is available through the URAT field. The URAT field is only reset by the SWRST bit in the CTRL register. |