26.8.4 Interrupt Enable Register
| Name: | IER |
| Offset: | 0x10 |
| Reset: | 0x00000000 |
| Property: | Write-Only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| URAD | |||||||||
| Access | W | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| RSU[3:0] | REC[3:0] | ||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RWC[3:0] | RBE[3:0] | ||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RDM[3:0] | RHC[3:0] | ||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 24 – URAD Undefined Register Access Detection Interrupt Enable
0: No effect
1: The Undefined Register Access interrupt is enabled.
Bits 23:20 – RSU[3:0] Region Status Updated Interrupt Enable
0: No effect
1: When RSU[i] is written to ‘1’, the region i Status Updated interrupt is enabled.
Bits 19:16 – REC[3:0] Region End bit Condition Detected Interrupt Enable
0: No effect
1: When REC[i] is written to ‘1’, the region i End bit Condition interrupt is enabled.
Bits 15:12 – RWC[3:0] Region Wrap Condition detected Interrupt Enable
0: No effect
1: When RWC[i] is written to ‘1’, the Region i Wrap Condition interrupt is enabled.
Bits 11:8 – RBE[3:0] Region Bus Error Interrupt Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | When RBE[i] is written to '1', the Region i Bus Error interrupt is enabled. |
Bits 7:4 – RDM[3:0] Region Digest Mismatch Interrupt Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | When RDM[i] is written to '1', the Region i Digest Mismatch interrupt is enabled. |
Bits 3:0 – RHC[3:0] Region Hash Completed Interrupt Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | When RHC[i] is written to '1', the Region i Hash Completed interrupt is enabled. |