39.6.3 Timestamp Generation

For timestamp generation, the CAN supplies a 16-bit wrap-around counter. A prescaler TSCC.TCP can be configured to clock the counter in multiples of CAN bit times (1…16). The counter is readable through TSCV.TSC. A write access to TSCV register resets the counter to ‘0’. When the timestamp counter wraps around interrupt flag IR.TSW is set.

On start of frame reception/transmission the counter value is captured and stored into the timestamp section of an Rx Buffer/Rx FIFO (RXTS[15:0]) or Tx Event FIFO (TXTS[15:0]) element.