53.6.2.4 Input Selection and Filtering

The QDEC and HALL operations require three inputs, as illustrated in the figure below.. Each input can either be a dedicated I/O pin or an Event system channel. This is selected by writing to the corresponding Event x Enable bit in the Event Control register (EVCTRL.EVEIx) or Pin x Enable bit in the Control A register (CTRLA.PINENx).

The I/O input pin active level can be inverted by writing to the corresponding Pin x Inversion Enable bit in the Control A register (CTRLA.PINVENx). Similarly, the event input active level can be inverted by writing to the corresponding Inverted Event x Input Enable bit in Event Control register (EVCTRL.EVINVx).

All input signals can be filtered before they are fed into the control logic. The FILTER register is used to configure the minimum duration for which the input signal has to be valid. The input signal minimum duration must be (FILTER+1)* tGCLK_PDEC .

Figure 53-3. Input Signal Filtering

Only the first two input signals can be swapped by writing to the SWAP bit in the Control A register (CTRLA.SWAP).