54.14.6 PCC Characteristics

Speed requirements for all 8/10/12/14-bits are:
  • pclk: 48 MHz at 3.3V
  • pclk: 28 MHz at 1.8V

APB clock minimum is 2 × N pclk

Figure 54-21. PCC Signaling
Figure 54-22. PCC - Peripheral Capture Controller Timing Diagrams
Table 54-64. PCC - Peripheral Capture Controller Electrical Specifications (4)
AC CHARACTERISTICSStandard Operating Conditions: VDDIO=VDDANA 1.71V to 3.63V (unless otherwise stated)

-40°C ≤ TA ≤ +125°C

Param. No.SymbolCharacteristicsMin.TypicalMax.UnitsConditions
PCC1PCC_CLKExternal PCC Data Input Clock Period20——nsVDDIOx(min)
PCC3PCCHIGHPCC Data Clock input High time10——ns
PCC5PCCLOWPCC Data Clock input Low time10——ns
PCC7PCCDSETUPClock to Data Setup Time3——ns
PCC9PCCDHOLDClock to Data Hold Time2——ns
PCC11PCCDENBSETUP (2)Data Enable [1,2] Setup Time (2)3——ns
PCC13PCCDENBHOLD (3)Data Enable [1,2] Hold Time (3)2
PCC15CLK_APB_PCC(1)Internal MCLK PCC Module Clock (1)——fCPUMhz
Note:
  1. CLK_APB_PCC ≥ (2 * PCC_CLK).
  2. PCCDENBSETUP ≥ PCC7.
  3. PCCDENBHOLD ≥ PCC9.
  4. These values are based on simulation. They are not covered by production test limits or characterization.