2.11.3 TX Interrupt
The UART Transmit UTXISEL[1:0] bits = ‘0b10 Interrupt is generated but
does not remain asserted while the transmit buffer is empty. When the IFS bit is cleared
by the user, it does not remain asserted even while the transmit buffer is empty. This
behavior, compounded with finite interrupt latency, can create a race condition amongst
subsequent TX interrupts.
Work Around
To avoid the race condition, clear the UARTx IFS flag before writing a new value to the TX Buffer, UxTXREG, in the ISR.
Affected Silicon Revisions
| A0 | A1 | B0 | C0 |
|---|---|---|---|
| X | X | X | X |