2.11.1 TX/RX Interrupt

A UART Transmit Interrupt (UTXISEL[1:0] bits (UxSTA[15:14]) = ‘0b00) is generated and asserted while the transmit buffer contains at least one empty space and the UART Receiver Interrupt Flag bit (URXISEL[1:0] bits (UxSTA[7:6]) = ‘0b00) is asserted while the receive buffer is not empty and non-functional.