2.11.5 RX Interrupt
The UART Receive Interrupt Flag bit (URXISEL[1:0] bits = ‘0b10) is
asserted only when the receive buffer equals three-quarters full and not when the
receive buffer is greater than three-quarters full.
Work Around
Before exiting the UART RX ISR, make sure the entire contents of the RX buffer were read by reading the contents of the RX buffer in the ISR until the URXDA bit (UxSTA[10]) is cleared and this work around is implemented in Harmony.
Affected Silicon Revisions
| A0 | A1 | B0 | C0 |
|---|---|---|---|
| X | X | X | X |