26.1 Fundamental Operation
The PWM module produces a 10-bit resolution output. The timer selection for PWMx is TMRx. TxTMR and TxPR set the period of the PWM. The PWMxDCL and PWMxDCH registers configure the duty cycle. The period is common to all PWM modules, whereas the duty cycle is independently controlled.
All PWM outputs associated with Timerx are set when TxTMR is cleared. Each PWMx is cleared when TxTMR is equal to the value specified in the corresponding PWMxDCH (8 MSb) and PWMxDCL[7:6] (2 LSb) registers. When the value is greater than or equal to TxPR, the PWM output is never cleared (100% duty cycle).