The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is
dedicated to the support of both the asynchronous and synchronous EUSART operations. By
default, the BRG operates in 8-bit mode. Setting the BRG16
bit selects 16-bit mode.
The SPxBRGH:SPxBRGL register pair determines the period of the
free-running baud rate timer. In Asynchronous mode, the multiplier of the baud rate period
is determined by both the BRGH
and the BRG16 bits. In Synchronous mode, the BRGH bit is ignored.
Table 30-1 contains the formulas for determining the baud rate. Equation 30-1 provides a sample calculation for determining the baud rate and baud
rate error.
Typical baud rates and error values for various Asynchronous modes
have been computed and are shown in the table below. It may be advantageous to use the high
baud rate (BRGH = 1), or the 16-bit BRG (BRG16 =
1) to reduce the baud rate error. The 16-bit BRG
mode is used to achieve slow baud rates for fast oscillator frequencies. The BRGH bit is
used to achieve very high baud rates.
Writing a new value to the SPxBRGH:SPxBRGL register pair causes the
BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer
overflow before outputting the new baud rate.
If the system clock is changed during an active receive operation, a
receive error or data loss may result. To avoid this, check the status of the Receive Idle
Flag (RCIDL) bit to make sure the receive operation is idle before changing the system
clock.
Table 30-1. Baud Rate Formulas
Configuration Bits
BRG/EUSART Mode
Baud Rate Formula
SYNC
BRG16
BRGH
0
0
0
8-bit/Asynchronous
FOSC/[64 (n+1)]
0
0
1
8-bit/Asynchronous
FOSC/[16 (n+1)]
0
1
0
16-bit/Asynchronous
0
1
1
16-bit/Asynchronous
FOSC/[4 (n+1)]
1
0
x
8-bit/Synchronous
1
1
x
16-bit/Synchronous
Note: x = Don’t
care, n = value of SPxBRGH:SPxBRGL register pair.
Table 30-2. Sample Baud Rates for Asynchronous Modes
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