9.6.2 Linear Data Memory
The linear data memory is the region from FSR address 0x2000 to FSR address 0x2FEF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Refer to Figure 9-20 for the Linear Data Memory Map.
Important: The address range
0x2000 to 0x2FEF represents the complete addressable Linear Data Memory for
PIC® devices (up to Bank 50). The actual implemented Linear Data
Memory will differ from one device to the other in a family.
Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank.
The 16 bytes of common memory are not included in the linear data memory region.