13.1 Sleep Mode Operation

Sleep mode is entered by executing the SLEEP instruction.

Upon entering Sleep mode, the following conditions exist:

  1. Resets other than WDT are not affected by Sleep mode; WDT will be cleared but keeps running if enabled for operation during Sleep.
  2. The PD bit is cleared.
  3. The TO bit is set.
  4. The CPU and the System clocks are disabled.
  5. LFINTOSC and/or HFINTOSC will remain enabled if any peripheral has requested them as a clock source or if the HFOEN, MFOEN or LFOEN bits are set.
  6. ADC is unaffected if the ADCRC oscillator is selected. When the ADC clock is something other than ADCRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains active.
  7. I/O ports maintain the status they had before SLEEP was executed (driving high, low, or high-impedance) only if no peripheral connected to the I/O port is active.

Refer to individual sections for more details on peripheral operation during Sleep.

To minimize current consumption, the following conditions need to be considered:

  • I/O pins will not be floating
  • External circuitry sinking current from I/O pins
  • Internal circuitry sourcing current from I/O pins
  • Current draw from pins with internal weak pull-ups
  • Modules using any oscillator

I/O pins that are high-impedance inputs need to be pulled to VDD or VSS externally to avoid switching currents caused by floating inputs.