38.2.1 Standard Instruction Set


n ∈ [ 0, 1]

The signed 6-bit literal ‘k’ is added to the contents of the FSRnH:FSRnL register pair.
FSRn is limited to the range 0000h-FFFFh. Moving beyond these bounds will cause the FSR to wrap-around.

d ∈ [0,1]

Add the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register.
If ‘d’ is ‘1’, the result is stored back in register ‘f’.

d ∈ [0,1]

Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is placed in data memory location ‘f’.

The contents of W are AND’ed with the 8-bit literal ‘k’.
The result is placed in W.

d ∈ [0,1]

AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register.
If ‘d’ is ‘1’, the result is stored back in register ‘f’.

d ∈ [0,1]

(f[7]) → dest[7]

(f[7:1]) → dest[6:0]

(f[0]) → C

The contents of register ‘f’ are shifted one bit to the right through the Carry flag.
The MSb remains unchanged.
If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is stored back in register ‘f’.

Register f → C

0 ≤ b ≤ 7

[ label ] BRA $+k

-256 ≤ k ≤ 255

Add the signed 9-bit literal ‘k’ to the PC.
Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + k.
This instruction is a two-cycle instruction. This branch has a limited range.

Add the contents of W (unsigned) to the PC.
Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + (W).
This instruction is a two-cycle instruction.

0 ≤ b ≤ 7

0 ≤ b ≤ 7

If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the next instruction is discarded,
and a NOP is executed instead, making this a two-cycle instruction.

0 ≤ b < 7

If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is executed.
If bit ‘b’ is ‘1’, then the next instruction is discarded,
and a NOP is executed instead, making this a two-cycle instruction.

k → PC[10:0],

(PCLATH[6:3]) → PC[14:11]

Call Subroutine. First, return address (PC + 1) is pushed onto the stack.
The 11-bit immediate address is loaded into PC bits [10:0].
The upper bits of the PC are loaded from PCLATH.
CALL is a two-cycle instruction.

(W) → PC[7:0],

(PCLATH[6:0]) → PC[14:8]

Subroutine call with W.
First, the return address (PC + 1) is pushed onto the return stack.
Then, the contents of W is loaded into PC[7:0], and the contents of PCLATH into PC[14:8].
CALLW is a two-cycle instruction.

1 → Z

1 → Z

00h → WDT prescaler,

1 → TO,

1 → PD

The CLRWDT instruction resets the 
Watchdog Timer.
It also resets the prescaler of the WDT.
Status bits, TO and PD, are set.

d ∈ [0,1]

The contents of register ‘f’ are complemented.
If ‘d’ is ‘0’, the result is stored in W.
If ‘d’ is ‘1’, the result is stored back in register ‘f’.

d ∈ [0,1]

Decrement register ‘f’.
If ‘d’ is ‘0’, the result is stored in the W register.
If ‘d’ is ‘1’, the result is stored back in register ‘f’.

d ∈ [0,1]

skip if result = 0

The contents of register ‘f’ are decremented.
If ‘d’ is ‘0’, the result is placed in the W register.
If ‘d’ is ‘1’, the result is placed back in register ‘f’.
If the result is ‘1’, the next instruction is executed.
If the result is ‘0’, then a NOP is executed instead,
making it a two-cycle instruction.

PCLATH[6:3] → PC[14:11]

GOTO is an unconditional branch.
The 11-bit immediate value is loaded into PC bits [10:0].
The upper bits of PC are loaded from PCLATH[4:3].
GOTO is a two-cycle instruction.

d ∈ [0,1]

The contents of register ‘f’ are incremented.
If ‘d’ is ‘0’, the result is placed in the W register.
If ‘d’ is ‘1’, the result is placed back in register ‘f’.

d ∈ [0,1]

skip if result = 0

The contents of register ‘f’ are incremented.
If ‘d’ is ‘0’, the result is placed in the W register.
If ‘d’ is ‘1’, the result is placed back in register ‘f’.
If the result is ‘1’, the next instruction is executed.
If the result is ‘0’, a NOP is executed instead,
making it a two-cycle instruction.

The contents of W are ORed with the 8-bit literal ‘k’.
The result is placed in W.

d ∈ [0,1]

Inclusive OR the W register with register ‘f’.
If ‘d’ is ‘0’, the result is placed in the W register.
If ‘d’ is ‘1’, the result is placed back in register ‘f’.

d ∈ [0,1]

(f[6:0]) → dest[7:1]

0 → dest[0]

The contents of register ‘f’ are shifted one bit to the left through the Carry flag.
A ‘0’ is shifted into the LSb.
If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is stored back in register ‘f’.

C ← Register f ← 0

d ∈ [0,1]

(f[7:1]) → dest[6:0],

(f[0]) → C

The contents of register ‘f’ are shifted one bit to the right through the Carry flag.
A ‘0’ is shifted into the MSb.
If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is stored back in register ‘f’.

0 → Register f → C

d ∈ [0,1]

The contents of register f is moved to a destination dependent upon the status of d.
If d = 0, destination is W register.
If d = 1, the destination is file register f itself.
d = 1 is useful to test a file register since status flag Z is affected.

MOVF   FSR, 0

[ label ] MOVIW --FSRn

[ label ] MOVIW FSRn++

[ label ] MOVIW FSRn--

[ label ] MOVIW k[FSRn]

mm ∈ [00,01,10,11]

-32 ≤ k ≤ 31

INDFn → (W)

This instruction is used to move data between W and one of the indirect registers (INDFn).
Before/after this move, the pointer (FSRn) is updated by pre/post incrementing/decrementing it.
The INDFn registers are not physical registers.
Any instruction that accesses an INDFn register actually accesses the register at the address specified by the FSRn.
FSRn is limited to the range 0000h - FFFFh.
Incrementing/decrementing it beyond these bounds will cause it to wrap-around.

The 8-bit literal ‘k’ is loaded into W register.
The “don’t cares” will assemble as ‘0’s.

MOVLW

MOVWF

[ label ] MOVWI --FSRn

[ label ] MOVWI FSRn++

[ label ] MOVWI FSRn--

[ label ] MOVWI k[FSRn]

mm ∈ [00,01,10,11]

-32 ≤ k ≤ 31

(W) → INDFn

This instruction is used to move data between W and one of the indirect registers (INDFn).
Before/after this move, the pointer (FSRn) is updated by pre/post incrementing/decrementing it.
The INDFn registers are not physical registers.
Any instruction that accesses an INDFn register actually accesses the register at the address specified by the FSRn.
FSRn is limited to the range 0000h-FFFFh.
Incrementing/decrementing it beyond these bounds will cause it to wrap-around.
The increment/decrement operation on FSRn will not affect any Status bits.

Execute a device Reset.
Resets the RI flag of the PCON register.

1 → GIE

Return from Interrupt.
Stack is POPed and Top-of-Stack (TOS) is loaded in the PC.
Interrupts are enabled by setting the Global Interrupt Enable bit, GIE (INTCON[7]).
This is a two-cycle instruction.

RETFIE  

(TOS) → PC,

The W register is loaded with the 8-bit literal ‘k’.
The program counter is loaded from the top of the stack (the return address).
This is a two-cycle instruction.

 	CALL TABLE			; W contains table
; offset value
; W now has
; table value
   :
TABLE
ADDWF PC			; W = offset
RETLW k1			; Begin table
RETLW k2			;
:
:
RETLW kn			; End of table

Return from subroutine.
The stack is POPped and the top of the stack (TOS) is loaded into the Program Counter.
This is a two-cycle instruction.

d ∈ [0,1]

(f[7]) → C,

(C) → dest[0]

The contents of register ‘f’ are rotated one bit to the left through the Carry flag.
If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default).

RLF

d ∈ [0,1]

(f[0]) → C,

(C) → dest[7]

The contents of register ‘f’ are rotated one bit to the right through the Carry flag.
If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default).

0 → WDT prescaler,

1 → TO,

0 → PD

The Power-Down (PD) Status bit is cleared.
The Time-Out (TO) Status bit is set.
Watchdog Timer and its prescaler are cleared.

The W register is subtracted (two’s complement method) from the 8-bit literal ‘k’.
The result is placed in the W register.

C = 0, W > k

C = 1, W ≤ k

DC = 0, W[3:0] > k[3:0]

DC = 1, W[3:0] ≤ k[3:0]

d ∈ [0,1]

Subtract (two’s complement method) W register from register ‘f’.
If ‘d’ is ‘0’, the result is stored in the W register.
If ‘d’ is ‘1’, the result is stored back in register ‘f.

C = 0, W > f

C = 1, W ≤ f

DC = 0, W[3:0] > f[3:0]

DC = 1, W[3:0] ≤ f[3:0]

d ∈ [0,1]

Subtract W and the Borrow flag (Carry) from register ‘f’ (two’s complement method).
If ‘d’ is ‘0’, the result is stored in W.
If ‘d’ is ‘1’, the result is stored back in register ‘f’.

d ∈ [0,1]

(f[7:4]) → dest[3:0]

The upper and lower nibbles of register ‘f’ are exchanged.
If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is placed in register ‘f’ (default).

Move data from W register to TRIS register.
When ‘f’ = 5, TRISA is loaded.
When ‘f’ = 6, TRISB is loaded.
When ‘f’ = 7, TRISC is loaded.

The contents of W are XORed with the 8-bit literal ‘k’.
The result is placed in W.

d ∈ [0,1]

Exclusive OR the contents of the W register with register ‘f’.
If ‘d’ is ‘0’, the result is stored in the W register.
If ‘d’ is ‘1’, the result is stored back in register ‘f’.