| Added automotive content
throughout |
| Reference Document |
New section |
| 1 Configuration Summary |
Updated Table 1-1 |
| 2 Block Diagram |
Updated Figure 2-1 |
| 6 Event System |
Updated Real-Time
Event List |
| 7 Package and Pinout |
Updated BGA343
Pinout |
| 8 System Interconnect and Security
(SIS) |
Table 8-12: added note (1) |
| 13 Bus Matrix (MATRIX) |
Removed “Security of Peripheral Bus Clients” section and MATRIX_SPSELRX
registers
Updated No Default Host, Slot Cycle
Limit Arbitration
|
| 14 DMA Controller (XDMAC) |
Updated Description, Figure 14-5
Embedded Characteristics: corrected embedded FIFO value
XDMAC_CC: modified reset value
XDMAC_GTYPE: modified XDMAC2 reset value
|
| 16 Static Memory Controller (SMC) |
Throughout: added Data Float Output Time content
Updated Block Diagram, I/O Lines
Description
Memory
Connection for an 8-bit Data Bus, Memory
Connection for a 16-bit Data Bus, Connection
of 2 x 8-bit Devices on a 16-bit Bus: Byte Write Option: added
note
SMC
Connections to Static Memory Devices to Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or
from Normal Mode to Slow Clock Mode: updated signal names in all
diagrams (no changes to waveforms)
HSMC_MODE: added PS field
HSMC_ELPRIM, HSMC_MODE, HSMC_PMECCx: modified reset values
|
| 17 Universal DDR Memory Controller
(UDDRC) |
Embedded Characteristics: updated list of
standards High-Level SDRAM Initialization Procedure, Step
5: corrected “ZQ calibration error check” sub-step Updated
Per-Bank Refresh (LPDDR2/LPDDR3 only), DLL-Off Mode
(DDR3) |
| 18 DDR/LPDDR Physical Interface (DDR3PHY) |
Throughout: editorial changes; modified signal names
Updated Embedded Characteristics, Byte Lane
PHY
Added Impedance Calibration
Register Summary: DDR3PHY_MR0_DDR, DDR3PHY_MR1_DDR deleted
DDR3PHY_ZQ0CR1: updated ZPROG field description
DDR3PHY_PGCR: index [28:25] now reserved; index [8:5] now
reserved
DDR3PHY_ODTCR: indexes [4,8,12,20,24,28] now reserved
DDR3PHY_DTDR0: DTBYTE0 now at index [7:0]
DDR3PHY_PGCR: RANKEN bit description updated
DDR3PHY_BISTRR: index 20 now reserved
Modified reset values for DDR3PHY_PGCR, DDR3PHY_DLLGCR, DDR3PHY_ACIOCR, DDR3PHY_ODTCR, DDR3PHY_BISTLSR, DDR3PHY_BISTAR1, DDR3PHY_BISTAR2, DDR3PHY_BISTUDPR, DDR3PHY_ZQ0CR0, DDR3PHY_ZQ0CR1, DDR3PHY_ZQ0SR0, DDR3PHY_DXxGCR, DDR3PHY_DXxDLLCR, DDR3PHY_DXxDQTR, DDR3PHY_DXxDQSTR
|
| 20 SYSTEM CONTROLLER SUBSYSTEM |
Updated Special
Functions in SFR/SFRBU |
| 21 System Controller Write Protection
(SYSCWP) |
Corrected Table 21-1
|
| 22 General Purpose Backup Registers (GPBR) |
Updated Description, Embedded
Characteristics
GPBR_FCLR: updated register description; updated FCLR description
|
| 23 Dual Watchdog Timer (DWDT) |
NS_WDT_MR and PW_WDT_MR: corrected WDDBGHLT and WDIDLEHLT positions
PS_WDT_VR: modified reset value
|
| 24 Reset Controller (RSTC) |
Updated Embedded Characteristics
RSTC_MR: added ENGCLR at index 20 and bit description
RSTC_SR: modified reset value
|
| 25 Real-Time Timer (RTT) |
Updated Figure 25-2
RTT_TSR: added TS_OVF bit; corrected TSTAMP field width
|
| 26 Real-Time Clock (RTC) |
All occurrences of Persian mode deleted
Updated Waveform Generation, RTC
Accurate Clock Calibration
RTC_MR: index 1 now ‘reserved’. Bit UTC, index 2, updated
RTC_SR: modified reset value
|
| 27 Shutdown Controller (SHDWC) |
SHDWC
Block Diagram: removed FWKUP pin
SHDW_MR: modified reset value
|
| 29 Chip Identifier (CHIPID) |
Embedded Characteristics, CHIPID_CIDR: modified Chip ID reset value |
| 30 OTP Memory Controller (OTPC) |
Updated Power
Management |
| 31 Special Function Registers (SFR) |
SFR_HSS_AXIQOS: updated WRITE and READ
descriptions |
| 32 Special Function Registers Backup (SFRBU) |
Register Summary: address offset 0x0C now 'reserved'
|
| 33 Slow Clock Controller (SCKC) |
Updated Embedded
Characteristics |
| 35 Power Management Controller (PMC) |
Throughout: changed “FSTP” to “WIP”
Updated Main Crystal Oscillator Failure Detection, Figure 35-6, Recommended Programming Sequence, Fast
Start-Up, Main System Bus Clock Controller, 32.768 kHz
Crystal Oscillator
CKGR_MOR: removed BMCKIC and BMCKRST bits
PMC_GCSR2: added GPID95 and GPID94 bits
PMC_FSMR: removed WLAN bits
PMC_MCKLIM: removed MCK_HIGH_RES and MCK_LOW_RES fields
CKGR_MOR, PMC_XTALF: modified reset values
|
| 36 Parallel Input/Output Controller (PIO) |
Inputs: added note
|
| 38 Analog-to-Digital Converter (ADC)
Controller |
Added Disabling the Temperature Sensor to Put the System in Low-Power
Mode
Updated Temperature Sensor, Buffer Structure, Buffer
Structure without FIFO, Buffer
Structure with FIFO, Input-Output Transfer Functions
Automatic Error Correction: updated value of Gs
ADC_TEMPMR: updated TEMPON
ADC_FMR: updated CHUNK description
ADC_ACR: index [9:8] now populated (IBCTL)
ADC_MR: modified reset value
ADC_EMR: updated OSR description
ADC_TRGR: updated TRGPER description
ADC_CVR: updated GAINCORR description
|
| 39 Analog Comparator Controller (ACC) |
ACC_ISR: modified reset value
|
| 41 Camera Serial Interface (CSI) |
Throughout: register short names and register bits renamed from DPHY to PHY
except for register CSI_DPHY_RSTZ; bit descriptions updated
Block
Diagram: deleted descriptive text below figure
Signal Description renamed to I/O Lines
Description
Updated Shutdown Mode, Interrupts
Register Summary: offsets 0x10, 0x14, 0x0130, 0x0134 now
'reserved'; offsets 0xE8, 0xF8, 0x0108, 0x0118, 0x0128 now populated (
CSI_INT_FORCE_PHY_FATAL, CSI_INT_FORCE_PKT_FATAL, CSI_INT_FORCE_FRAME_FATALCSI_INT_FORCE_PHY, CSI_INT_FORCE_PKT)
CSI_INT_ST_MAIN: bit index 18 now 'reserved'
CSI_PHY_TEST_CTRL1: added PHY_TESTDOUT at index [15:8]
CSI_INT_ST_PKT, CSI_INT_MSK_PKT: register names modified
|
| 42 CSI-2 Demultiplexer Controller (CSI2DC) |
Updated Functional Description, CSI2DC Block
Diagram, Figure 42-3
CSI2DC_VPDTRR: updated access
CSI2DC_GSPS0R, CSI2DC_GSPS1R,
CSI2DC_GSPS2R, CSI2DC_GSPS3R:
modified reset values
CSI2DC_SSPISR, CSI2DC_GSPISR, CSI2DC_GLPISR, CSI2DC_IDSISR, CSI2DC_DPISR, CSI2DC_VPISR: updated bit descriptions
|
| 43 Image Sensor Controller (ISC) |
Throughout: added register write protection information
Descriptor Memory Mapping: updated column “Address” in Table 43-4, Table 43-5, Table 43-6
Added Scaler Function
Clock
Domain Diagram: added synchronization signals
ISC_DCTRL: updated DVIEW description
ISC_CLKSR: modified reset value
ISC_DST0, ISC_DST1, ISC_DST2: index 16:31 now ‘ reserved’
ISC_INTEN, ISC_INTDIS, ISC_INTMASK. ISC_INTSR: added bit WPE at index 30 and bit description
|
| 45 Inter-IC Sound Multi-Channel Controller (I2SMCC) |
Corrected “I2SMCC_SCK” to “I2SMCC_CK”, and “SCK” to “CK”
Added Pad Hysteresis Control
Updated I2S Reception and Transmission Sequence, Left-Justified Reception and Transmission Sequence, DMA
Controller Operation, Common
Registers
Product
Dependencies: added note
TX DMA Chunk Configurations, RX DMA Chunk Configurations: updated column titles;
added note
I2SMCC_MRB: updated PACK24 description (note) and DMACHUNK
description
I2SMCC_MRB: I2SLINESIZE description updated for values 1 and
2
I2SMCC_ISRA: updated RXLRDYx and TXRRDYx descriptions
|
| 46 Synchronous Serial Controller (SSC) |
Added Audio Sampling Rate Limitations
Updated Register Write Protection
SSC_WPMR: updated WPEN description
|
| 47 Sony/Philips Digital Interface Receiver
(SPDIFRX) |
Updated Embedded Characteristics
SPDIFRX_RSR: modified reset value; updated ULOCK description
|
| 48 Sony/Philips Digital Interface Transmitter
(SPDIFTX) |
Updated Embedded Characteristics, Interrupt
Sources, Transmit FIFO, 9-bit to
16-bit Data, Write
Protection Registers
SPDIFTX_WPSR: updated WPVSRC description
SPDIFTX_EMR, SPDIFTX_ISR: modified reset values
Removed SPDIFTX_AW1 and SPDIFTX_AW2 registers and TXRDYCH1, TXRDYCH2,
TXUDR1, TXUDR2 bits
|
| 49 Pulse Density Microphone Controller (PDMC) |
Updated Embedded Characteristics, Block
Diagram, Pre-Filter, Figure 49-4, PDMC_ISR
PDMC_MR: modified reset value
PDMC_CR: added write protection information
|
| 50 Asynchronous Sample Rate Converter (ASRC) |
Updated Table 50-1
ASRC_TRIG: updated TRIGSELINx, TRIGSELOUTx descriptions
ASRC_VBPS_OUT: updated VBPS_OUTx description
ASRC_ESR: bits [31:16] now 'reserved'
ASRC_ISRx: modified reset value; updated RXCHUNK, TXCHUNK
descriptions
|
| 54 Advanced Encryption Standard (AES) |
AES_MR: modified reset value
|
| 56 Triple Data Encryption Standard (TDES) |
TDES_MR: modified reset value
|
| 57 Random Number Generator (TRNG) |
TRNG_WPSR: modified SWETYP description (value 5)
|
| 58 Integrity Check Monitor (ICM) |
ICM_ISR: updated bit descriptions (cleared on read)
|
| 60 Security Module (SECUMOD) |
SECUMOD_BMPR: added note on DETx bits
SECUMOD_WKPR: DETx now at index [21:18]; bits [17:16] reserved;
added note
SECUMOD_CR, SECUMOD_PIOBUx, SECUMOD_JTAGCR: modified reset value
|
| 61 CONNECTIVITY SUBSYSTEM |
Added Important Note
|
| 62 Gigabit Ethernet MAC (GMAC) |
Updated Receive Buffer List, Transmit
Buffer List
GMAC_DCFGR: corrected offset of bit CRCERRREP
GMAC_TQSA: updated SEGALLOCQx description
|
| 63 Flexible Serial Communication Controller (FLEXCOM) |
Changed “TWIHS_” to “FLEX_TWI_” throughout
Updated Bus Clear Command, FIFO
Pointer Error, USART
Asynchronous and Partial Wake-Up, Baud Rate
in Synchronous Mode, SPI
Comparison Function on Received Character, SPI
Asynchronous and Partial Wake-Up, TWI
Asynchronous and Partial Wake-Up, SCL Rising
Time Control, FLEX_TWI_CR
Sniffer
Mode: updated Sniffer description
FLEX_TWI_CR: added SCLRBD and SCLRBE at index 18 and 19,
respectively
FLEX_TWI_SR: modified reset value
FLEX_TWI_SMR: updated BSEL description
|
| 64 Quad Serial Peripheral Interface (QSPI) |
Throughout: changed “AHB” to “system bus”, and “APB” to “peripheral bus”;
corrected clock name from “GCK” to “GCLK”
Updated Signal Description, Twin-Quad
Mode
QSPI_SCR: updated DLYBS description
QSPI_MR: removed OENSD and QICMEN bits
QSPI_IFR: corrected NBDUM field size
|
| 65 Secure Digital MultiMedia Card Controller (SDMMC) |
SDMMC_CA0R: updated bit descriptions
SDMMC_PSR: modified reset value
|
| 66 Controller Area Network (MCAN) |
Updated Address Configuration, Timestamping, Timestamp
Generation
MCAN_TEST: updated RX bit description
|
| 67 Timer Counter (TC) |
Throughout: added explanatory notes about Timer Counter block instances
Updated Block Diagram
TC_BMR: updated TCxXCxS descriptions
|
| 68 Pulse Width Modulation Controller (PWM) |
Updated PWM_DEBUG, PWM_SMMR, PWM_ETRGx, PWM_LEBRx, Figure 68-16
Description, Embedded
Characteristics, Fault Protection, PWM_FPE: modified number of fault inputs
|
| 72 USB Device High Speed Port (UDPHS) |
Transfer Without DMA: modified code content
UDPHS_INTSTA: editorial changes
|
| 74 Electrical Characteristics |
Updates throughout, mainly: Minor fixes on figures |
| 75 Mechanical Characteristics |
Added Table 75-1, Table 75-2, Table 75-3, Table 75-4 |
| 76 Marking |
Corrected Jedec symbol |
