66.6.5 MCAN CC Control Register
| Name: | MCAN_CCCR |
| Offset: | 0x18 |
| Reset: | 0x00000001 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| NISO | TXP | EFBI | PXHD | BRSE | FDOE | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TEST | DAR | MON | CSR | CSA | ASM | CCE | INIT | ||
| Access | R/W | R/W | R/W | R/W | R | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
Bit 15 – NISO Non-ISO Operation
If this bit is set, the MCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0.
| Value | Description |
|---|---|
| 0 | CAN FD frame format according to ISO11898-1 (default). |
| 1 | CAN FD frame format according to Bosch CAN FD Specification V1.0. |
Bit 14 – TXP Transmit Pause (write protection)
If this bit is set, the MCAN pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Tx Handling).
| Value | Description |
|---|---|
| 0 | Transmit pause disabled. |
| 1 | Transmit pause enabled. |
Bit 13 – EFBI Edge Filtering during Bus Integration (write protection)
| Value | Description |
|---|---|
| 0 |
Edge filtering is disabled. |
| 1 |
Edge filtering is enabled. Two consecutive dominant tq required to detect an edge for hard synchronization. |
Bit 12 – PXHD Protocol Exception Event Handling (write protection)
| Value | Description |
|---|---|
| 0 |
Protocol exception handling enabled. |
| 1 |
Protocol exception handling disabled. |
Bit 9 – BRSE Bit Rate Switching Enable (write protection)
0 (DISABLED): Bit rate switching for transmissions disabled.
1 (ENABLED): Bit rate switching for transmissions enabled.
Bit 8 – FDOE CAN FD Operation Enable (write protection)
0 (DISABLED): FD operation disabled.
1 (ENABLED): FD operation enabled.
Bit 7 – TEST Test Mode Enable (write protection against ‘1’)
0 (DISABLED): Normal operation, MCAN_TEST register holds reset values.
1 (ENABLED): Test mode, write access to MCAN_TEST register enabled.
Bit 6 – DAR Disable Automatic Retransmission (write protection)
0 (AUTO_RETX): Automatic retransmission of messages not transmitted successfully enabled.
1 (NO_AUTO_RETX): Automatic retransmission disabled.
Bit 5 – MON Bus Monitoring Mode (write protection against ‘1’)
0 (DISABLED): Bus Monitoring mode is disabled.
1 (ENABLED): Bus Monitoring mode is enabled.
Bit 4 – CSR Clock Stop Request
0 (NO_CLOCK_STOP): No clock stop is requested.
1 (CLOCK_STOP): Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle.
Bit 3 – CSA Clock Stop Acknowledge
| Value | Description |
|---|---|
| 0 | No clock stop acknowledged. |
| 1 | MCAN may be set in power down by stopping the peripheral clock and the CAN core clock. |
Bit 2 – ASM Restricted Operation Mode (write protection against ‘1’)
For a description of the Restricted Operation mode see Restricted Operation Mode.
0 (NORMAL): Normal CAN operation.
1 (RESTRICTED): Restricted Operation mode active.
Bit 1 – CCE Configuration Change Enable (write protection)
0 (PROTECTED): The processor has no write access to the protected configuration registers.
1 (CONFIGURABLE): The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = ‘1’).
Bit 0 – INIT Initialization
Due to the synchronization mechanism between the two clock domains, there may be a delay until the value written to INIT can be read back. Therefore the programmer has to ensure that the previous value written to INIT has been accepted by reading INIT before setting INIT to a new value.
0 (DISABLED): Normal operation.
1 (ENABLED): Initialization is started.