66.6.43 MCAN Transmit Event FIFO Configuration
This register can only be written if the bits CCE and INIT are set in MCAN CC Control Register.
| Name: | MCAN_TXEFC |
| Offset: | 0xF0 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| EFWM[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| EFS[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EFSA[13:6] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EFSA[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bits 29:24 – EFWM[5:0] Event FIFO Watermark
| Value | Description |
|---|---|
| 0 | Watermark interrupt disabled. |
| 1-32 | Level for Tx Event FIFO watermark interrupt (MCAN_IR.TEFW). |
| >32 |
Watermark interrupt disabled. |
Bits 21:16 – EFS[5:0] Event FIFO Size
The Tx Event FIFO elements are indexed from 0 to EFS - 1.
| Value | Description |
|---|---|
| 0 | Tx Event FIFO disabled. |
| 1-32 | Number of Tx Event FIFO elements. |
| >32 |
Values greater than 32 are interpreted as 32. |
Bits 15:2 – EFSA[13:0] Event FIFO Start Address
Start address of Tx Event FIFO in Message RAM (32-bit word address, see Message RAM Configuration).
Write EFSA with the bits [15:2] of the 32-bit address.