The flowcharts shown in this section provide examples for read and
write operations. A polling or interrupt method can be used to check the status bits. The
interrupt method requires that the Interrupt Enable register (FLEX_TWI_IER) be configured
first.
Figure 63-97. TWI Write Operation with Single Data Byte without Internal
AddressFigure 63-98. TWI Write Operation with Single Data Byte and Internal
AddressFigure 63-99. TWI Write Operation with Multiple Data Bytes with or without
Internal AddressFigure 63-100. SMBus Write Operation with Multiple Data Bytes with or
without Internal Address and PEC SendingFigure 63-101. SMBus Write Operation with Multiple Data Bytes with PEC and
Alternative Command ModeFigure 63-102. TWI Write Operation with Multiple Data Bytes and Read
Operation with Multiple Data Bytes (Sr)Figure 63-103. TWI Write Operation with Multiple Data Bytes + Read Operation
and Alternative Command Mode + PECFigure 63-104. TWI Read Operation with Single Data Byte without Internal
AddressFigure 63-105. TWI Read Operation with Single Data Byte and Internal
AddressFigure 63-106. TWI Read Operation with Multiple Data Bytes with or without
Internal AddressFigure 63-107. TWI Read Operation with Multiple Data Bytes with or without
Internal Address with PECFigure 63-108. TWI Read Operation with Multiple Data Bytes with Alternative
Command Mode with PECFigure 63-109. TWI Read Operation with Multiple Data Bytes + Write Operation
with Multiple Data Bytes (Sr)Figure 63-110. TWI Read Operation with Multiple Data Bytes + Write with
Alternative Command Mode with PEC
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