27.7.2 SHDWC Mode Register

Name: SHDW_MR
Offset: 0x04
Reset: 0x00100000
Property: Read/Write

This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode register (SYSC_WPMR).

Bit 3130292827262524 
      WKUPDBC[2:0] 
Access R/WR/WR/W 
Reset 000 
Bit 2322212019181716 
    AUTOLPM  RTCWKENRTTWKEN 
Access WR/WR/W 
Reset 100 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
          
Access  
Reset  

Bits 26:24 – WKUPDBC[2:0] Wake-up Inputs Debouncer Period

ValueNameDescription
0 IMMEDIATE Immediate, no debouncing, detected active at least on one MD_SLCK edge
1 3_SLCK PIOBUx shall be in its active state for at least 3 MD_SLCK periods
2 32_SLCK PIOBUx shall be in its active state for at least 32 MD_SLCK periods
3 512_SLCK PIOBUx shall be in its active state for at least 512 MD_SLCK periods
4 4096_SLCK PIOBUx shall be in its active state for at least 4,096 MD_SLCK periods
5 32768_SLCK PIOBUx shall be in its active state for at least 32,768 MD_SLCK periods

Bit 20 – AUTOLPM Automatic LPM Pad Management

ValueDescription
0 The LPM pad is never automatically modified by the RSTC.
1 The LPM pad is automatically modified by the RSTC when the system goes into or out of the ULP2 mode.

Bit 17 – RTCWKEN Real-time Clock Wake-up Enable

ValueDescription
0 The RTC Alarm signal has no effect on the SHDWC.
1 The RTC Alarm signal forces the de-assertion of the SHDN pin.

Bit 16 – RTTWKEN Real-time Timer Wake-up Enable

ValueDescription
0 The RTT Alarm signal has no effect on the SHDWC.
1 The RTT Alarm signal forces the de-assertion of the SHDN pin.