27.7.3 SHDWC Status Register
| Name: | SHDW_SR |
| Offset: | 0x08 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| WKUPIS5 | WKUPIS4 | WKUPIS3 | WKUPIS2 | WKUPIS1 | WKUPIS0 | ||||
| Access | R | R | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| LPM | |||||||||
| Access | R | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RTCWK | RTTWK | WKUPS | |||||||
| Access | R | R | R | ||||||
| Reset | 0 | 0 | 0 |
Bits 16, 17, 18, 19, 20, 21 – WKUPISx Wake-up x Input Status
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE |
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. |
| 1 | ENABLE |
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event. |
Bit 8 – LPM Low-Power Mode Pad Status
| Value | Description |
|---|---|
| 0 |
The LPM pad is currently set to 0. |
| 1 |
The LPM pad is currently set to 1. |
Bit 5 – RTCWK Real-time Clock Wake-up
| Value | Description |
|---|---|
| 0 |
No wake-up alarm from the RTC occurred since the last read of SHDW_SR. |
| 1 |
At least one wake-up alarm from the RTC occurred since the last read of SHDW_SR. |
Bit 4 – RTTWK Real-time Timer Wake-up
| Value | Description |
|---|---|
| 0 |
No wake-up alarm from the RTT occurred since the last read of SHDW_SR. |
| 1 |
At least one wake-up alarm from the RTT occurred since the last read of SHDW_SR. |
Bit 0 – WKUPS PIOBU, WKUP Wake-up Status
| Value | Name | Description |
|---|---|---|
| 0 | NO |
No wake-up due to the assertion of PIOBU, WKUP pins has occurred since the last read of SHDW_SR. |
| 1 | PRESENT |
At least one wake-up due to the assertion of PIOBU, WKUP pins has occurred since the last read of SHDW_SR. |