26.6.9 RTC Calendar Alarm Register (UTC_MODE)

This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode register (SYSC_WPMR).

Name: RTC_CALALR (UTC_MODE)
Offset: 0x14
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
        UTCEN 
Access R/W 
Reset 0 

Bit 0 – UTCEN UTC Alarm Enable

ValueNameDescription
0 DISABLED

The UTC-matching alarm is disabled.

1 ENABLED

The UTC-matching alarm is enabled.