26.6.11 RTC Status Clear Command Register
To avoid missing clearing commands, wait for three slow clock cycles between two accesses to this register.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Clears the corresponding status flag in the Status register (RTC_SR).
| Name: | RTC_SCCR |
| Offset: | 0x1C |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TDERRCLR | CALCLR | TIMCLR | SECCLR | ALRCLR | ACKCLR | ||||
| Access | W | W | W | W | W | W | |||
| Reset | – | – | – | – | – | – |
Bit 5 – TDERRCLR Time and/or Date Free Running Error Clear
If the RTC is configured in UTC mode, this bit has no effect.
Bit 4 – CALCLR Calendar Clear
If the RTC is configured in UTC mode, this bit has no effect.
Bit 3 – TIMCLR Time Clear
If the RTC is configured in UTC mode, this bit has no effect.