26.6.22 RTC TimeStamp Source Register

This register is cleared after read and the read access also performs a clear on RTC_TSTRx and RTC_TSDRx.

The following configuration values are valid for all listed bit names of this register:

0: No alarm generated since the last clear.

1: An alarm has been generated by the corresponding monitor since the last clear.

Name: RTC_TSSRx
Offset: 0xB8 + x*0x0C [x=0..1]
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
   DET3DET2DET1DET0   
Access RRRR 
Reset 0000 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
     JTAGTST DWDTSW 
Access RRR 
Reset 000 

Bits 18, 19, 20, 21 – DETx PIOBU Intrusion Detector (cleared on read)

Bit 3 – JTAG JTAG Pins Monitor (cleared on read)

Bit 2 – TST Test Pin Monitor (cleared on read)

Bit 0 – DWDTSW Dual WatchDog Timer Event (cleared on read)