50.5.4 Embedded Digital PLL

Each DSP embeds a digital PLL (DPLL) for precise estimation of the sampling points.

The embedded DPLL precisely computes the ratio between the input and the output sampling rates to obtain a high-quality output signal.

The DSP must be disabled (ASRC_MR.ASRCENx=0) if both input and output sampling rates are not established, as the DPLL continuously computes the sampling rate difference between the input and the output audio streams.