24.4.2.4 ULP Mode 2 Reset

The ULP Mode 2 reset is entered when a WFE event occurs while CKGR_MOR.ULP2 is set to ‘1’ in the PMC.

When this reset occurs, only the Processor reset is asserted. The VDDCPU power supply can be switched off during the ULP mode 2 (refer to “ULP Mode 2” in the section “Power Management Controller (PMC)”.