70.6.1 Battery Charging

The Battery Charging Specification defines the charger detection hardware to be controlled.

The features defined in the Battery Charging Specification can be controlled using TCPC_UPC and the resulting outputs can be observed in TCPC_UPS as shown in the table and figure that follow.

Table 70-2. Battery Charging Specification to USB PHY Mapping
Battery Charging Specification Reference	TCPC Register Field
Data Contact Detect I_{DP_SRC} Current Source Enable	TCPC_UPC.BCIDPSRCE
Data Contact Detect R_{DM_DWN} Pull-Down Control	Force activation: TCPC_UPC.DMPDFE Force deactivation: TCPC_UPC.DMPDFD
Primary Detection or Secondary Detection	Select detection type: TCPC_UPC.BCDETSEL
Primary / Secondary Detection V_{DP_SRC} / V_{DM_SRC} Voltage Source Enable	TCPC_UPC.BCVSRCE
Primary / Secondary Detection CHG_DET / DCHG_DET⁽¹⁾ Comparator Enable	TCPC_UPC.BCDETE
Primary / Secondary Detection CHG_DET / DCHG_DET⁽¹⁾ Comparator Output	TCPC_UPS.CHGDCP
Data Contact Detect D+ line state	TCPC_UPS.DP

Note:

In the Battery Charging Specification, DCHG_DET indicates DCP_DET comparator output in a Portable Device (PD) and indicates PRTBL_DET comparator output in a Charging Downstream Port (CDP).

Figure 70-2. Charger Detection Hardware

After any software change in the Control register (TCPC_UPC) or after any change on the USB D+ line state, the charger detection outputs in the Status register (TCPC_UPS) may not be valid before an update delay, as shown in the Max Delay Update column of the table below.

These update delays must be respected after any TCPC_UPC software change when implementing the Data Contact Detect and Primary / Secondary Detection of the “Charger Detection Algorithms” specified in the Battery Charging Specification.

Changes to TCPC_UPS register bits are filtered to avoid USB D+ line state glitches propagation. The maximum glitch duration that is always filtered is shown in the Min Glitch Filtering column in the table below.

Any longer filtering or debouncing, such as during the t_{DCD_DBNC} time for the D+ line as specified in the Battery Charging Specification (see Reference Documents), must be performed by periodically sampling TCPC_UPS.

Table 70-3. TCPC_UPS Glitch Filtering Times
TCPC_UPS Bit	Max Delay Update	Min Glitch Filtering
TCPC_UPS.DP	560 μs	450 μs
TCPC_UPS.CHGDCP	140 μs	30 μs