43.6.3 BT.601/656/1120 Embedded Timing Synchronization Operation

The ISC module supports embedded synchronization decoding. When ISC_PFE_CFG0.CCIR656 is set, the decoder is activated and signals isc_vsync and isc_hsync are not used to decode the valid pixels. If CCIR10_8N is set, the bitstream is 10 bits wide, otherwise it is only 8 bits wide. When ISC_PFE_CFG0.CCIR_CRC is set, the decoder automatically corrects the error.

Figure 43-13. Field/Segment Timing Relationship for Interlaced and Segmented Frame Systems

Figure 43-14. Frame Timing Relationship for Progressive Systems

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