43.6.1 ISC Clock Management
The ISC module provides the ISC_MCK output clock to the CSI2 Demultiplexer Controller (CSI2DC), which transfers video stream from the MIPI CSI2 clock domain to the ISC_MCK clock domain. See the Block Diagram.
ISC_MCK has one programmable clock divider (ISC_CLKCFG.MCDIV). The clock is enabled using ISC_CLKEN.MCEN.
The ISC is designed to accept input signals that are asynchronous to hclock.
Synchronization is done internally as long as the following relationship holds:
- isc_pck frequency is lower than or equal to hclock frequency.