62.6.3.3 Receive Buffers

Received frames, optionally including FCS, are written in receive buffers located in system memory. The receive buffer depth is programmable in the range of 64 bytes to 16320 bytes. If received frames are being routed to different priority queues (via the packet inspection screeners – see section Priority Queuing in the DMA), it is possible to program different receive buffer depths for each queue. For queue 0, the receive buffer depth is programmed through the DMA Configuration register (offset 0x10). For the other queues, they are programmed in the independent queue configuration registers (starting from offset 0x4a0). The default is 128 bytes.

The start location for each receive buffer is stored in system memory in a list of receive buffer descriptors at an address location pointed to by the receive buffer queue pointer. The base address for the receive buffer queue pointer is configured in software using the Receive Buffer Queue Base Address register.

The number of words in each buffer descriptor (BD) is dependent on the operating mode.

Each buffer descriptor (BD) word is defined as 32 bits.

The first two words (Word 0 and Word 1) are used for all BD modes. In Extended Buffer Descriptor modes (GMAC_DCFGR.RXDB_EXTENDED = 1), two BD words are added for 64-bit addressing mode and two BD words are added for timestamp capture.There are therefore either two, four or six BD words in each BD entry depending on the operating mode, and every BD entry has the same number of words.

To summarize:

• Every descriptor is 64 bits wide when the descriptor Timestamp Capture mode is disabled.
• Every descriptor is 128 bits wide when the descriptor Timestamp Capture mode is enabled.

The first is the address of the receive buffer and the second the receive status. If the length of a receive frame exceeds the buffer length, the status word for the used buffer is written with zeroes except for the “start of frame” bit, which is always set for the first buffer in a frame. Bit zero of the address field is written to 1 to show the buffer has been used. The receive buffer manager then reads the location of the next receive buffer and fills that with the next part of the received frame data. Receive buffers are filled until the frame is complete and the final buffer descriptor status word contains the complete frame status. See the table below for details of the receive buffer descriptor list.

Each receive buffer start location is a word address. The start of the first buffer in a frame can be offset by up to three bytes, depending on the value written to bits 14 and 15 of the Network Configuration register. For 64-bit datapaths, the start of the frame can be offset by up to a further four bytes if bit 2 of the buffer start location in the buffer descriptor is set. If the start location of the buffer is offset, the available length of the first buffer is reduced by the corresponding number of bytes.

To receive frames, the buffer descriptors must be initialized by writing an appropriate address to bits 31:2 in the first word of each list entry. Bit 0 must be written with zero. Bit 1 is the wrap bit and indicates the last entry in the buffer descriptor list.

The start location of the receive buffer descriptor list must be written with the receive buffer queue base address before reception is enabled (receive enable in the Network Control register). Once reception is enabled, any writes to the Receive Buffer Queue Base Address register are ignored. When read, it will return the current pointer position in the descriptor list, though this is only valid and stable when receive is disabled.

If the filter block indicates that a frame should be copied to memory, the receive data DMA operation starts writing data into the receive buffer. If an error occurs, the buffer is recovered.

The receive buffer queue pointer increments by two words after each buffer has been used. It re-initializes to the receive buffer queue base address if any descriptor has its wrap bit set.

As receive buffers are used, the receive buffer manager sets bit zero of the first word of the descriptor to logic one indicating the buffer has been used.

Software should search through the “used” bits in the buffer descriptors to find out how many frames have been received, checking the start of frame and end of frame bits.

When the DMA is configured in the packet buffer Partial Store And Forward mode, received frames are written out to the system bus buffers as soon as enough frame data exists in the packet buffer. For both cases, this may mean several full system bus buffers are used before some error conditions can be detected. If a receive error is detected the receive buffer currently being written will be recovered. Previous buffers will not be recovered. As an example, when receiving frames with cyclic redundancy check (CRC) errors or excessive length, it is possible that a frame fragment might be stored in a sequence of receive buffers. Software can detect this by looking for start of frame bit set in a buffer following a buffer with no end of frame bit set.

To function properly, a 10/100/1000 Ethernet system should have no excessive length frames or frames greater than 128 bytes with CRC errors. Collision fragments will be less than 128 bytes long, therefore it will be a rare occurrence to find a frame fragment in a receive buffer, when using the default value of 128 bytes for the receive buffers size.

When in packet buffer Full Store and Forward mode, only good received frames are written out of the DMA, so no fragments will exist in the system memory buffers due to MAC receiver errors. There is still the possibility of fragments due to DMA errors, for example used bit read on the second buffer of a multi-buffer frame.

If bit zero of the receive buffer descriptor is already set when the receive buffer manager reads the location of the receive buffer, then the buffer has been already used and cannot be used again until software has processed the frame and cleared bit zero. In this case, the “buffer not available” bit in the Receive Status register is set and an interrupt triggered. The Receive Resource Error statistics register is also incremented.

When the DMA is configured in the packet buffer Full Store and Forward mode, the user can optionally select whether received frames should be automatically discarded when no system bus buffer resource is available. This feature is selected via bit 24 of the DMA Configuration register (by default, the received frames are not automatically discarded). If this feature is off, then received packets will remain to be stored in the GMAC local memory packet buffer until the system memory buffer resource next becomes available. This may lead to an eventual packet buffer overflow if packets continue to be received when bit zero (used bit) of the receive buffer descriptor remains set. Note that after a used bit has been read, the receive buffer manager will re-read the location of the receive buffer descriptor every time a new packet is received. When the DMA is not configured in the packet buffer Full Store and Forward mode and a used bit is read, the frame currently being received will be automatically discarded.

When the DMA is configured in the packet buffer Full Store and Forward mode, a receive overrun condition occurs when the receive GMAC local memory packet buffer is full, or because the system bus returns an error. In all other modes, a receive overrun condition occurs when either the system bus was not granted quickly enough, or because of a system bus error, or because a new frame has been detected by the receive block, but the status update or write back for the previous frame has not yet finished. For a receive overrun condition, the receive overrun interrupt is asserted and the buffer currently being written is recovered. The next frame that is received whose address is recognized reuses the buffer.

In any packet buffer mode, a write to bit 18 of GMAC_NCR forces a packet from the external SRAM-based receive packet buffer to be flushed. This feature is only acted upon when the DMA receive channel is not currently writing packet data out to system bus. If the DMA receive channel is active, a write to this bit is ignored.