35.10.2.1 Configuration Procedure

Before configuring asynchronous partial wake-up for a peripheral, check that the PIDx bit in PMC_CSR is set. This ensures that the peripheral clock is enabled.

The steps to enable asynchronous partial wake-up for a peripheral are the following:

1. Check that PMC_SLPWKCR.ASR is set to ‘0’ for the corresponding peripheral. This ensures that the peripheral has no activity in progress.
2. Enable asynchronous partial wake-up for the peripheral by writing a ‘1’ to PMC_SLPWKCR.SLPWKSR.
3. Check that PMC_SLPWKCR.ASR is set to '0'. This ensures that no activity has started during the enable phase.

   If PMC_SLPWKCR.ASR=1, proceed to the next step.

   If PMC_SLPWKCR.ASR=0, Asynchronous Partial Wake-up mode is active for the peripheral. Before entering ULP1 or ULP2 mode, check that the AIP bit in the Asynchronous Partial Wake-Up Activity In Progress register (PMC_SLPWK_AIPR) is cleared. This ensures that the peripheral has no activity in progress due to a reactivation.

4. In PMC_SLPWKCR, asynchronous partial wake-up must be immediately disabled by writing a ‘0’ to SLPWKSR. Wait for the end of peripheral activity before reinitializing the procedure.