35.10.3.1 Configuration Procedure

Before configuring the asynchronous partial wake-up function of a peripheral, check that the PIDx bit in PMC_CSR is set. This ensures that the peripheral clock is enabled.

The steps to enable the asynchronous partial wake-up function of a peripheral are the following:

  1. Check that PMC_SLPWKCR.ASR is set to ‘0’. This ensures that the peripheral has no activity in progress.
  2. Enable the asynchronous partial wake-up function of the peripheral by writing a ‘1’ to PMC_SLPWK_ER.SLPWKSR.
  3. Check that PMC_SLPWKCR.ASR is set to '0'. This ensures that no activity has started during the enable phase.

    If PMC_SLPWKCR.ASR=1, proceed to the next step.

    If PMC_SLPWKCR.ASR=0, Asynchronous Partial Wake-up mode is active for the peripheral. Before entering ULP1 or ULP2 mode, check that the AIP bit in the PMC Asynchronous Partial Wake-Up Activity In Progress register (PMC_SLPWK_AIPR) is cleared. This ensures that the peripheral has no activity in progress due to a reactivation.

  4. In PMC_SLPWKCR, asynchronous partial wake-up must be immediately disabled by writing a ‘0’ to SLPWKSR. Wait for the end of peripheral activity before reinitializing the procedure.
Note: If an activity has started during the enable phase, the asynchronous partial wake-up function must be immediately disabled by writing a ‘0’ to PMC_SLPWKCR.SLPWKSR. Wait for the end of peripheral activity before reinitializing the procedure.When asynchronous partial wake-up for a peripheral is enabled and the core is running (system not in ULP1 or ULP2 mode), the peripheral must not be accessed before a wake-up of the peripheral is performed.