10.6.1 Interrupt Line Characteristics

For each event source, the EIC features a dedicated interrupt line as shown in the Block Diagram.

If Glitch Filter Enable (GFEN) is cleared in the Source Configuration register (EIC_SCFGxR), pulses of any width can be forwarded and detected as valid source events on the interrupt line x regardless of the respective frequencies of the source clock, the EIC peripheral clock and the Interrupt Controller clock.

If EIC_SCFGxR.GFEN is set, the source events are filtered to remove unwanted glitches. The glitch filter forwards its input level when it is maintained for more than 2^GFSEL peripheral clock cycles and rejects pulses narrower than 2^GFSEL-1 peripheral clock cycles.

The source event polarity can be changed by EIC_SCFGxR.POL.

Either edge or level event detection can be performed by EIC_SCFGxR.LVL.

When set, EIC_SCFGxR.FRZ freezes all interrupt line settings until hardware reset. This includes the settings in EIC_SCFGxR. This feature can be used to prevent any corruption of the critical interrupt lines configuration.

If the glitch filter is enabled in EIC_SCFGxR.GFEN, the maximum propagation delay through the EIC (see the following figure) is calculated as:

$\text{EIC\_delay\_max}=\text{(2 + 2GFSEL) * periph\_clk\_period}+\text{2.5 * clock\_period}$

and the minimum propagation delay through the EIC is:

$\text{EIC\_delay\_min}=\text{(1 + 2GFSEL) * periph\_clk\_period}+\text{1 * clock\_period}$

If the glitch filter is disabled, the maximum propagation delay through the EIC is calculated as:

$\text{EIC\_delay\_max}=\text{2.5 * clock\_period}$

and the minimum propagation delay through the EIC is:

$\text{EIC\_delay\_min}=\text{1 * clock\_period}$

clock_period is the peripheral clock period of the EIC as programmed in the Power Management Controller.