74.10.2.2 SDRAM Self-Refresh Mode

SDRAM devices require paced refreshes to maintain data consistency. These refreshes are paced by the DDR_CLK signal. To reduce system frequency or disable DDR_CLK, the SDRAM device must be put in Self-refresh mode.

Self-refresh deactivates the SDRAM clock and automatically executes a refresh operation using the SDRAM device internal refresh counter. Self-refresh mode is effective when the device is not accessed for a long time and the data must be kept for a future use (for context saving or peripheral configurations to recover current system state for example).

As the SDRAM device is not accessed, SDRAM I/Os are configured in Retention state:

  • DDR_CLK tied to 0
  • DDR_CLKN tied to 0
  • DDR_CSN tied to 1

This is the case in some SAMA7G5 low-power modes such as Backup Self-refresh, ULP1 and ULP2. These modes use the following routines. Code example is provided in software deliverables.

Entering SDRAM Self-Refresh Mode

  1. Save the first eight 32-bit SDRAM words in the backup SRAM.
  2. Save the calibration result in the backup SRAM.
  3. Set the static values for DDR_CLK and DDR_CLKN to 0,0 when the pair is disabled.
  4. Perform a Data Synchronization Barrier (DSB).
  5. Disable all UDDRC ports.
    • Wait for port disable to complete.
  6. Move system to Self-refresh state.
    • Wait until Self-refresh is entered.
  7. Put the DDR3PHY BYTE DLLs in Bypass mode.
  8. Power down the DDR3PHY data receivers.
  9. Power down the Address Control, Clock, Chip Select and ODT pin output drivers.
Entering Self-Refresh Mode with I/O Power-down
  1. Save the first eight 32-bit SDRAM words in the backup SRAM.
  2. Save the calibration result in the backup SRAM.
  3. Set the static values for DDR_CLK and DDR_CLKN to 0,0 when the pair is disabled.
  4. Perform a Data Synchronization Barrier (DSB).
  5. Disable all UDDRC ports.
    • Wait for port disable to complete.
  6. Move system to Self-refresh state.
    • Wait until Self-refresh is entered.
  7. Power down the DDR3PHY data receivers.
  8. Power down the Clock and Chip Select pin output drivers.
  9. Power down the Address Control and ODT pin output drivers.
  10. Set the SDRAM I/Os to Retention state by setting SFRBU_DDRPWR.RETENTION.

Exiting SDRAM Self-Refresh Mode

  1. Power down the CK and CS pin output drivers.
  2. Power down the ODT[3:0] pin I/Os output drivers in the UDDRC DFI Low Power Configuration register 0 (UDDRC_DFILPCFG0).
  3. Power down the data input receiver I/Os.
  4. Move the DDR3PHY BYTE DLLs out of Bypass mode.
  5. In the UDDRC Software Register Programming Control Enable (UDDRC_SWCTL) register, enable quasi-dynamic register programming.
  6. Clear the UDDRC_DFIMISC.DFI_INIT_COMPLETE_EN bit.
  7. Set UDDRC_SWCTL.SW_DONE to indicate that UDDRC programming is completed.
    • Poll the UDDRC_SWSTAT.SW_DONE_ACK bit until it changes to 1, acknowledging that programming is complete.
  8. Perform a DDR3PHY DLL soft reset , and DLL Lock and ITM soft reset commands.
    • Wait for completion.
  9. In the UDDRC_SWCTL register, enable quasi-dynamic register programming.
  10. Set the DDRC_DFIMISC.DFI_INIT_COMPLETE_EN bit.
  11. Set UDDRC_SWCTL.SW_DONE to indicate that UDDRC programming is completed.
    • Poll the UDDRC_SWSTAT.SW_DONE_ACK bit until it changes to 1, acknowledging that programming is complete.
  12. Trigger self-refresh exit.
    • Wait until Self-refresh state is exited.
  13. Enable the five AXI ports with the UDDRC_PCTRL_x.PORT_EN bits.
  14. Recover the first eight 32-bit SDRAM words from the backup SRAM.
  15. Recover the calibration result from the backup SRAM.