16.17.3 NFC Initialization

Prior to any Command and Data Transfer, the SMC User Interface must be configured to meet the device timing requirements.

  • Write Enable Configuration

Use NWE_SETUP, NWE_PULSE and NWE_CYCLE to define the write enable waveform according to the external device datasheet.

Use HSMC_TIMINGS.TADL to configure the timing between the last address latch cycle and the first rising edge of WEN for data input.

Figure 16-33. Write Enable Timing Configuration
Figure 16-34. Write Enable Timing for NAND Flash Device Data Input Mode
  • Read Enable Configuration

Use NRD_SETUP, NRD_PULSE and NRD_CYCLE to define the read enable waveform according to the external device datasheet.

Use HSMC_TIMINGS.TAR to configure the timings between the address latch enable falling edge to read the enable falling edge.

Use HSMC_TIMINGS.TCLR to configure the timings between the command latch enable falling edge to read the enable falling edge.

Figure 16-35. Read Enable Timing Configuration Working with NAND Flash Device
  • Ready/Busy Signal Timing Configuration with a NAND Flash Device

Use HSMC_TIMINGS.TWB to configure the maximum elapsed time between the rising edge of the wen signal and the falling edge of the Ready/Busy signal. Use TRR field in the HSMC_TIMINGS register to program the number of clock cycles between the rising edge of the Ready/Busy signal and the falling edge of the ren signal.

Figure 16-36. Ready/Busy Timing Configuration