48.6.2 SPDIF Transmitter FIFO

The controller embeds one 32-element FIFO per channel. The FIFO is organized in bytes so that the selected data format is optimized.

The status of the FIFOs is reported in the Interrupt Status register (SPDIFTX_ISR).

The FIFO can be filled while the SPDIFTX is disabled.

The status flags of the two FIFOs are merged into one status register. Thus, a ready flag is raised only if the two FIFOs are ready. An error flag is raised if at least one of the two FIFOs has an error.