48.6.5 Transmit FIFO

Each channel embeds a 32-word FIFO to handle the data to be transmitted (words are defined on 24 bits). The depth of the FIFO varies with the size of the audio words defined by SPDIFTX_MR.BPS. The size of the FIFO in bytes is 32 multiplied by three. The number of bytes that are written into the FIFO depends on the word size (SPDIFTX_MR.BPS) and on the transfer mode (SPDIFTX_MR.CMODE).

As long as the TXRDY flag of a channel in the SPDIF Transmitter Channel Status register is active, the SPDIFTX controller is ready to accept one data through SPDIFTX_CDR. Data which cannot be converted immediately are stored in the FIFO of the corresponding channel.

If the FIFO of one channel is full, the TXFULL flag rises and the TXRDY flag is inactive.

If the system writes data in SPDIFTX_CDR while the TXFULL flag is high, an overrun occurs. The data is not written in the FIFO and the TXOVR flag rises.

If the FIFO of one channel is empty, the TXEMPTY flag is raised.

If the system fails to send data while the TXEMPTY flag is raised, an underrun occurs. The last transmitted data is sent again and the TXUDR flag is raised. As long as TXEMPTY flag is set invalid frames will be sent (with validity bit set to ‘1’). It is possible to disable invalid frame sending while the TXEMPTY flag is active by setting the SPDIFTX_MR.DNFR bit to ‘1’.

A threshold can also be defined to know when the FIFO is ready to receive an amount of data defined by SPDIFTX_MR.CHUNK. The threshold is defined as a number of accesses to SPDIFTX_CDR.

This chunk definition can be used with the DMA to define how many access can be performed. In this case, the chunk size that is chosen must match the chunk value defined in the DMA.