24.5.2 RSTC Status Register

Name: RSTC_SR
Offset: 0x04
Reset: 0x00000001
Property: Read-only

The reset value assumes that a general reset has been performed, subject to change if other types of reset are generated.

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
       SRCMPNRSTL 
Access RR 
Reset 00 
Bit 15141312111098 
     RSTTYP[3:0] 
Access RRRR 
Reset 0000 
Bit 76543210 
        URSTS 
Access R 
Reset 1 

Bit 17 – SRCMP Software Reset Command in Progress

When set, indicates that a software reset command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset.

ValueDescription
0

No software command is being performed by the RSTC. The RSTC is ready for a software command.

1

A software reset command is being performed by the RSTC. The RSTC is busy.

Bit 16 – NRSTL NRST Pin Level

Registers the NRST pin level sampled on each MCK rising edge.

Bits 11:8 – RSTTYP[3:0] Reset Type

Reports the cause of the last processor reset. Reading RSTC_SR does not reset this field.

ValueNameDescription
0 GENERAL_RST

First power-up reset

1 BACKUP_RST

Return from Backup mode

2 WDT_RST

Watchdog fault occurred

3 SOFT_RST

Processor reset required by the software

4 USER_RST

NRST pin detected low

5

Reserved

6 Reserved
7 SLCK_XTAL_RST

32.768 kHz crystal failure detection fault occurred

8 ULP2_RST

ULP Mode 2 reset

Bit 0 – URSTS User Reset Status

A high-to-low transition of the NRST pin sets URSTS. This transition is also detected on the MCK rising edge. If the user reset is disabled (RSTC_MR.URSTEN = 0) and if the interrupt is enabled by RSTC_MR.URSTIEN, URSTS triggers an interrupt. Reading RSTC_SR resets URSTS and clears the interrupt.

ValueDescription
0

No high-to-low edge on NRST happened since the last read of RSTC_SR.

1

At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.