24.5.3 RSTC Mode Register

This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR).

Name: RSTC_MR
Offset: 0x08
Reset: 0x00000001
Property: Read/Write

Bit 3130292827262524 
 KEY[7:0] 
Access WWWWWWWW 
Reset 0000000 
Bit 2322212019181716 
    ENGCLR     
Access R/W 
Reset 0 
Bit 15141312111098 
     ERSTL[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
    URSTIEN URSTASYNCSCKSWURSTEN 
Access R/WR/WR/WR/W 
Reset 0001 

Bits 31:24 – KEY[7:0] Write Access Password

ValueNameDescription
0xA5 PASSWD Writing any other value in this field aborts the write operation. Always reads as 0.

Bit 20 – ENGCLR Enable GPBR Clear on Tamper Event

ValueDescription
0 Disables the GPBR immediate clear on tamper detection event.
1 Enables the GPBR immediate clear on tamper detection event

Bits 11:8 – ERSTL[3:0] External Reset Length

This field defines the external reset length. The external reset pin RST_OUT is asserted during a time of 2(ERSTL+1) MD_SLCK cycles. This allows assertion duration to be programmed between 60 μs and 2 seconds. Note that synchronization cycles must also be considered when calculating the actual reset length as previously described.

Bit 4 – URSTIEN User Reset Interrupt Enable

ValueDescription
0 RSTC_SR.USRTS at ‘1’ has no effect on the RSTC interrupt line.
1 RSTC_SR.USRTS at ‘1’ asserts the RSTC interrupt line if URSTEN = 0.

Bit 2 – URSTASYNC User Reset Asynchronous Control

See NRST Signal or Interrupt for important information on the use of URSTASYNC.
ValueDescription
0 The NRST input signal is managed synchronously.
1 The NRST input signal is managed asynchronously.
Note: This mode cannot be selected if the external bus interface drives an SDR/DDR memory device and another memory on the same bus.

Bit 1 – SCKSW Slow Clock Switching

ValueDescription
0 The detection of a 32.768 kHz crystal failure has no effect.
1 The detection of a 32.768 kHz crystal failure resets the logic supplied by VDDCORE.

Bit 0 – URSTEN User Reset Enable

ValueDescription
0 The detection of a low level on the NRST pin does not generate a user reset.
1 The detection of a low level on the NRST pin triggers a user reset.