24.5.3 RSTC Mode Register
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR).
| Name: | RSTC_MR |
| Offset: | 0x08 |
| Reset: | 0x00000001 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| KEY[7:0] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | – | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| ENGCLR | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ERSTL[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| URSTIEN | URSTASYNC | SCKSW | URSTEN | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 1 |
Bits 31:24 – KEY[7:0] Write Access Password
| Value | Name | Description |
|---|---|---|
| 0xA5 | PASSWD | Writing any other value in this field aborts the write operation. Always reads as 0. |
Bit 20 – ENGCLR Enable GPBR Clear on Tamper Event
| Value | Description |
|---|---|
| 0 | Disables the GPBR immediate clear on tamper detection event. |
| 1 | Enables the GPBR immediate clear on tamper detection event |
Bits 11:8 – ERSTL[3:0] External Reset Length
This field defines the external reset length. The external reset pin RST_OUT is asserted during a time of 2(ERSTL+1) MD_SLCK cycles. This allows assertion duration to be programmed between 60 μs and 2 seconds. Note that synchronization cycles must also be considered when calculating the actual reset length as previously described.
Bit 4 – URSTIEN User Reset Interrupt Enable
| Value | Description |
|---|---|
| 0 | RSTC_SR.USRTS at ‘1’ has no effect on the RSTC interrupt line. |
| 1 | RSTC_SR.USRTS at ‘1’ asserts the RSTC interrupt line if URSTEN = 0. |
Bit 2 – URSTASYNC User Reset Asynchronous Control
| Value | Description |
|---|---|
| 0 | The NRST input signal is managed synchronously. |
| 1 | The NRST
input signal is managed asynchronously. Note: This mode cannot be selected if
the external bus interface drives an SDR/DDR memory device and another memory
on the same bus. |
Bit 1 – SCKSW Slow Clock Switching
| Value | Description |
|---|---|
| 0 | The detection of a 32.768 kHz crystal failure has no effect. |
| 1 | The detection of a 32.768 kHz crystal failure resets the logic supplied by VDDCORE. |
Bit 0 – URSTEN User Reset Enable
| Value | Description |
|---|---|
| 0 | The detection of a low level on the NRST pin does not generate a user reset. |
| 1 | The detection of a low level on the NRST pin triggers a user reset. |