31.7 UDDRC Register

Name: SFR_UDDRC
Offset: 0x202C
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
        DIS_DECERR 
Access R/W 
Reset 0 

Bit 0 – DIS_DECERR Disable Decode Error

ValueDescription
0

Enables decode error when reading a non-existing register in the DDR controller Configuration Address Space.

1

Disables decode error when reading a non-existing register in the DDR controller Configuration Address Space.